SYSTEM AND METHOD FOR CONVERTING SOFTWARE TO A REGISTER TRANSFER (RTL) DESIGN

• US 20090144690A1
• Filed: 11/30/2007
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: CebaTech, Inc.
• Inventors: Lipke, Lawrence, Spackman, Chad, Port, Adrian
• Granted Patent: US 7,904,850 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

Claims

1. A method for converting program code that is not in a hardware description language (HDL) to hardware, said program code including an algorithmic representation of a process using variables, the method comprising the steps of:

compiling the program code into an HDL synthesizable design, said step of compiling includes the steps of;

categorizing each of said variables in said program code as using either a respective implicit memory or a respective custom memory,

when a respective variable of the variables in said program code is categorized as using the respective implicit memory, defining a first type of accessor function for accessing the respective implicit memory, and

when the respective variable in said program code is categorized as using the respective custom memory, defining a second type of accessor function for accessing the respective custom memory, the second type of access function being different from the first type of accessor function; and

generating the hardware including implementing, as hardware, the first and second accessor functions based on said HDL synthesizable design.

2. The method as in claim 1, wherein said respective implicit memory is a register file memory.

3. The method as in claim 1, wherein the program code further includes a further algorithmic representation of a further process;

the step of compiling the program code into the HDL synthesizable design includes the steps of;

defining a first HDL synthesizable module representing the process and a second HDL synthesizable module representing the further process,

dynamically allocating a pointer to a global variable of the variables, and

providing an interface function, which uses the dynamically allocated pointer, to define inputs and/or outputs for the global variable used by at least one of the first or second HDL synthesizable modules.

4. The method as in claim 1, further comprising the step of:

restructuring portions of first program code into the program code representing the process, the program code representing the process being coded to be non-terminating; and

mapping the input and output of the non-terminating program code representing the process to one of a global variable or a process queue such that variables are passed to the non-terminating program code through the global variable or the process queue.

5. The method as in claim 1, wherein said first type of accessor function defines, at least in part, a signal interface of the respective implicit memory, said signal interface including names and widths of signals, and identifies a timing model for the memory.

6. The method as in claim 5, wherein the timing model is a synchronization model.

7. The method as in claim 5, further comprising the step of:

defining, a lane access parameter, for accessing a subset of bits of the respective implicit memory, responsive to accessing the respective implicit memory; and

reading to or writing from the subset of bits of the respective implicit memory using the lane access parameter.

8. The method as in claim 1 wherein the program code is written in ANSI C program language and the HDL is Verilog Register Transfer Level (RTL).

9. The method as in claim 1, wherein said second type of accessor function defines a signal interface and timing model of the custom memory.

10. The method as in claim 1, further including the step of defining attributes of a compiler directive, wherein the step of categorizing each of said variable includes using said defined attributes of the compiler directive to establish the accessor function corresponding to the respective custom memory.

11. The method as in claim 1, wherein the custom memory includes off-chip custom memory external to the HDL synthesizable design and on-chip custom memory internal to the HDL synthesizable design.

12. The method as in claim 1 wherein, when said variable is categorized as using custom memory, and when said custom memory is off-chip custom memory that is external to the HDL synthesizable design, the method further comprises:

defining a foreign interface function as a series of assignment statements from memory output pins of the off-chip custom memory to corresponding static variables and from the static variables to corresponding input pins of the off-chip memory.

13. The method as in claim 1, wherein said HDL is Verilog Register Transfer Level (RTL) and wherein said hardware device is an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

14. A system for converting program code that is not in a hardware description language (HDL) to hardware, said program code including an algorithmic representation a process, the system comprising:

means for compiling the program code into an HDL synthesizable design, wherein said means for compiling includes;

means for categorizing each of said variables in said program code as using either a respective implicit memory or a respective custom memory,

means for accessing the respective implicit memory using a first type of accessor function when a respective variable in said program code is categorized as using the respective implicit memory, and

means for accessing the respective custom memory using a second type of accessor function, different from the first type of accessor function when the respective variable in said program code is categorized as using the respective custom memory; and

means for generating the hardware from the HDL synthesizable design.

15. A method of simulating hardware in program code using a multi-thread system, the program code including an algorithmic representation corresponding to the hardware, by executing a plurality of processes, comprising the steps of:

running each process in a separate thread of the multi-thread system;

declaring at least one directive for each separate thread of the multi-thread system; and

controlling, by each directive, a respective one of the separate threads to execute in a timed sequence relative to the other respective ones of the separate threads.

16. A multi-threaded system for simulating hardware in program code, the program code including an algorithmic representation corresponding to the hardware by executing a plurality of processes, comprising:

means for running each process in a separate thread of the multi-thread system;

means for declaring at least one directive for each separate thread of the multi-thread system; and

means for controlling, by execution of respective directives, each of the separate threads to execute at particular time such that respective ones of the separate threads execute in a sequence.

17. A method of simulating hardware in program code, the program code including an algorithmic representation corresponding to the hardware, comprising the steps of:

declaring a custom memory accessor function in the program code, the customer memory accessor function including a timing model for accessing a custom memory;

compiling the program code into a hardware description language (HDL) synthesizable design, said step of compiling includes the steps of;

categorizing at least one variable in said program code as using the custom memory; and

translating the timing model in the declared program code to access the custom memory using the custom memory accessor function.

18. A system for simulating hardware using program code that is not in a hardware description language (HDL), the program code including an algorithmic representation corresponding to the hardware by executing a plurality of processes, comprising:

means for declaring a custom memory accessor function in the program code, the customer memory accessor function including a timing model for accessing a custom memory;

means for compiling the program code into a hardware description language (HDL) synthesizable design, said means for compiling includes;

means for categorizing at least one variable in said program code as using the custom memory; and

means for translating the timing model in the declared program code to access the custom memory using the custom memory accessor function.

19. A method of generating Register Transfer Level (RTL) code from program code in an other program language not intended to produce RTL, to simulate hardware, comprising the steps of:

defining a renaming function directive for renaming variable names used in arguments of the program code;

receiving a predetermined name of a variable used in the program code that does not conform to program code naming standards;

declaring in a specified argument, the renaming function directive including the predetermined name, and a second name, which is to be associated with the predetermined name and which conforms to the program code naming standards;

compiling the program code in the other language including the steps of;

associating the predetermined name with the second name for the variable of the specified argument, and

processing the specified argument using the second name as the name of the variable; and

compiling the program code into the RTL code including the step of;

processing the specified argument using the first name as the name of the variable.

20. A system for generating Register Transfer Level (RTL) code from program code in an other program language not intended to produce RTL code, to simulate hardware, the program code receiving a predetermined name of a variable that does not conform to program code naming standards, comprising:

means for defining a renaming function directive for renaming variable names used in arguments of the program code;

means for declaring in a specified argument, the renaming function directive including the predetermined name, and a second name, which is to be associated with the predetermined name and which conforms to the program code naming standards;

means for compiling the program code in the other language including;

means for associating the predetermined name with the second name for the variable of the specified argument, and

means for processing the specified argument using the second name as the name of the variable; and

means for compiling the program code into the RTL code including;

means for processing the specified argument using the first name as the name of the variable.

21. A method for converting program code that is not in a hardware description language (HDL) to hardware, said program code including an algorithmic representation of a plurality of process, the method comprising the steps of:

compiling the program code into an HDL synthesizable design, said step of compiling includes the steps of;

defining a first HDL synthesizable module corresponding to a first one of the plurality of processes and a second HDL synthesizable module corresponding to a second one of the plurality of processes,

defining input/output ports for the first and second HDL synthesizable modules, and

defining an interface function to define inputs and/or outputs between the first and second one of the plurality of processes that map to the created input and output ports of the first and second HDL synthesizable modules; and

generating the hardware including implementing, as hardware, the first and second HDL synthesizable modules and interface function based on said HDL synthesizable design.

22. The method as in claim 21, wherein the interface function is shared between the first and second HDL synthesizable modules and defines an arbitrator to arbitrate priority of access through the shared interface function, the arbitrator including at least one of:

(1) a round robin arbitrator in which concurrent calls from the first HDL synthesizable module and second HDL synthesizable modules are cycled;

or (2) a priority arbitrator in which a priority value is assigned to each respective HDL synthesizable module and concurrent calls from the first HDL synthesizable modules and the second HDL synthesizable module are arbitrated by the priority arbitrator based on the assigned priority values.

23. The method as in claim 21, wherein:

the interface function is shared between the first and second HDL synthesizable modules;

the step of defining the interface function includes;

categorizing each variable in said program code which is shared by the first and second HDL synthesizable modules as using either implicit memory or custom memory,

when a respective variable which is shared by the first and second HDL synthesizable modules is categorized as using implicit memory, defining a first type of accessor function inside of the shared interface function for accessing a respective implicit memory from the first and second HDL synthesizable modules, and

when the respective variable which is shared by the first and second HDL synthesizable modules is categorized as using the custom memory, defining a second type of accessor function inside the shared interface function for accessing a respective custom memory from the first and second HDL synthesizable modules, the second type of access function being different from the first type of accessor function; and

generating the hardware including implementing, as hardware, the first and second accessor functions and the shared interface function based on said HDL synthesizable design.