CIRCUIT MEMBER, MANUFACTURING METHOD OF THE CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE INCLUDING THE CIRCUIT MEMBER

• US 20090146280A1
• Filed: 11/28/2006
• Published: 06/11/2009
• Est. Priority Date: 11/28/2005
• Status: Abandoned Application

• Current Assignee: Dai Nippon Printing Company Limited
• Original Assignee: Dai Nippon Printing Company Limited
• Inventors: Saito, Hiroyuki, Shimazaki, Yo, Matsumura, Kenji, Fukuchi, Masaru, Ikezawa, Takao, Masuda, Masachika
• Application Number:
  US12/095,014
• Publication Number:
  US 20090146280A1
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: C25D 5/12 at least one layer being of nickel or chromium
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85464 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 μm or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.

Claims

1. A circuit member comprising a lead frame material including a die pad, a lead part adapted to be electrically connected with a semiconductor chip to be mounted on the die pad, and an outer frame configured to support the die pad and the lead part, the lead frame material being formed from a rolled copper plate or a rolled copper-alloy plate,

wherein the lead frame material includes a resin sealing region to be sealed by a resin, together with the semiconductor chip mounted on the die pad,

wherein the lead frame material includes a roughened face, having an average roughness Ra of 0.3 μ

m or greater, formed on a surface in the resin sealing region of the lead frame material, and a flat and smooth face, having the average roughness Ra less than that of the roughened face, on a surface outside the resin sealing region of the lead frame material, and

wherein a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, is provided on a whole surface of the lead frame material.

2. The circuit member according to claim 1,

wherein the roughened face is formed on a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.

3. The circuit member according to claim 1,

wherein a thickness of the Ni plated layer is within a range of from 0.2 μ

m to 2 μ

m.

4. The circuit member according to claim 1,

wherein a thickness of the Pd plated layer is within a range of from 0.005 μ

m to 0.2 μ

m.

5. The circuit member according to claim 1,

wherein a thickness of the Au plated layer is within a range of from 0.003 μ

m to 0.015 μ

m.

6. The circuit member according to claim 1,

wherein the lead part is positioned so as to surround the die pad from four sides or to surround the die pad from opposite two sides, in a plane substantially the same as the die pad, and

wherein the lead part includes a plurality of lead line parts each extending from a portion in the vicinity of the die pad to the outside of the resin sealing region.

7. A circuit member comprising a lead frame material including a die pad, a lead part adapted to be electrically connected via a bonding wire with a semiconductor chip to be mounted on the die pad, and an outer frame configured to support the die pad and the lead part, the lead frame material being formed from a rolled copper plate or a rolled copper-alloy plate,

wherein the lead frame material includes a resin sealing region to be sealed by a resin, together with the semiconductor chip mounted on the die pad and the bonding wire,

wherein a single plated layer composed of an Ag plated layer, a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, is provided on a surface of the die pad opposed to the semiconductor chip as well as on a portion, to be connected with the bonding wire, of a surface of the lead part, and

wherein the lead frame material includes a roughened face formed on a portion, on which no plated layer is formed, of a surface in the resin sealing region of the lead frame material, the roughened face having an average roughness Ra of 0.3 μ

m or greater, and a flat and smooth face, having the average roughness Ra less than that of the roughened face, on a surface outside the resin sealing region of the lead frame material.

8. The circuit member according to claim 7,

wherein the plated layer is formed on a top surface of the die pad as well as on a portion, to be connected with the bonding wire, of a top surface of the lead part, and

wherein the roughened face is formed on a portion of a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.

9. The circuit member according to claim 7,

wherein a thickness of the Ni plated layer is within a range of from 0.2 μ

m to 2 μ

m.

10. The circuit member according to claim 7,

wherein a thickness of the Pd plated layer is within a range of from 0.005 μ

m to 0.2 μ

m.

11. The circuit member according to claim 7,

wherein a thickness of the Au plated layer is within a range of from 0.003 μ

m to 0.015 μ

m.

12. The circuit member according to claim 7,

wherein the lead part is positioned so as to surround the die pad from four sides or to surround the die pad from opposite two sides, in a plane substantially the same as the die pad, and

wherein the lead part includes a plurality of lead line parts each extending from a portion in the vicinity of the die pad to the outside of the resin sealing region.

13. A manufacturing method for a circuit member, comprising the steps of:

providing a lead frame material made from a rolled copper plate or a rolled copper-alloy plate, the lead frame material including a die pad, a lead part adapted to be electrically connected with a semiconductor chip to be mounted on the die pad, and an outer frame configured to support the die pad and the lead part;

forming a roughened face, having an average roughness Ra of 0.3 μ

m or greater, on a surface in a resin sealing region of the lead frame material by using a micro-etching liquid mainly containing hydrogen peroxide and sulfuric acid, the resin sealing region being adapted to be sealed by a resin together with the semiconductor chip mounted on the die pad; and

forming a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, on a whole surface of the lead frame material in which the roughened face is partially formed.

14. The manufacturing method for the circuit member according to claim 13,

wherein the roughened face is formed on a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.

15. The manufacturing method for the circuit member according to claim 13,

wherein the step of forming the roughened face includes the steps of:

holding the lead frame material from both sides, by using a jig configured to surround the resin sealing region of the lead frame material so as to mask a region outside the resin sealing region; and

discharging the micro-etching liquid into the jig from both sides of the lead frame material so as to fill the interior of the jig surrounding the resin sealing region of the lead frame material with the micro-etching liquid.

16. The manufacturing method for the circuit member according to claim 13,

wherein the step of forming the roughened face includes the steps of:

sticking protective films onto both sides of the lead frame material, each protective film having an opening formed therein to expose the resin sealing region of the lead frame material; and

injecting the micro-etching liquid toward the inside of the openings of the protective films from both sides of the lead frame material.

17. The manufacturing method for the circuit member according to claim 13,

wherein the step of forming the roughened face includes the steps of:

sticking protective films onto both sides of the lead frame material, each protective film having an opening formed therein to expose the resin sealing region of the lead frame material; and

immersing the lead frame material, with the protective films stuck onto the lead frame material, in the micro-etching liquid.

18. A manufacturing method for a circuit member, comprising the steps of:

providing a lead frame material made from a rolled copper plate or a rolled copper-alloy plate, the lead frame material including a die pad, a lead part adapted to be electrically connected via bonding wire with a semiconductor chip to be mounted on the die pad, and an outer frame configured to support the die pad and the lead part;

forming a single plated layer composed of an Ag plated layer, a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, on a surface of the die pad opposed to the semiconductor chip as well as on a portion, to be connected with the bonding wire, of a surface of the lead part; and

forming a roughened face having an average roughness Ra of 0.3 μ

m or greater on a portion, on which no plated layer is formed, of a surface in a resin sealing region of the lead frame material by using a micro-etching liquid mainly containing hydrogen peroxide and the sulfuric acid, the resin sealing region being adapted to be sealed by a resin, together with the semiconductor chip located on the die pad and the bonding wire.

19. The manufacturing method for the circuit member according to claim 18,

wherein the plated layer is formed on a top surface of the die pad as well as on a portion, to be connected with the bonding wire, of a top surface of the lead part, and

wherein the roughened face is formed on a portion of a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.

20. The manufacturing method for the circuit member according to claim 18,

wherein the step of forming the roughened face includes the steps of:

holding the lead frame material from both sides, by using a jig configured to surround the resin sealing region of the lead frame material so as to mask a region outside the resin sealing region; and

discharging the micro-etching liquid into the jig from both sides of the lead frame material so as to fill the interior of the jig surrounding the resin sealing region of the lead frame material with the micro-etching liquid.

21. The manufacturing method for the circuit member according to claim 18,

wherein the step of forming the roughened face includes the steps of:

sticking protective films onto both sides of the lead frame material, each protective film having an opening formed therein to expose the resin sealing region of the lead frame material; and

injecting the micro-etching liquid toward the inside of the openings of the protective films from both sides of the lead frame material.

22. The manufacturing method for the circuit member according to claim 18,

wherein the step of forming the roughened face includes the steps of:

sticking protective films onto both sides of the lead frame material, each protective film having an opening formed therein to expose the resin sealing region of the lead frame material; and

immersing the lead frame material, with the protective films stuck onto the lead frame material, in the micro-etching liquid.

23. A semiconductor device comprising:

a semiconductor chip;

a circuit member including a lead frame material having a die pad onto which the semiconductor chip is mounted, and a lead part electrically connected with the semiconductor chip located on the die pad, the lead frame material being formed from a rolled copper plate or a rolled copper-alloy plate;

a bonding wire electrically connecting the semiconductor chip located on the die pad with the lead part; and

an electrically insulating sealing resin sealing the circuit member, the semiconductor chip and the bonding wire, such that a portion of the lead part of the circuit member can be exposed,

wherein the lead frame material includes a resin sealing region sealed by the sealing resin, together with the semiconductor chip located on the die pad,

wherein the lead frame material includes a roughened face, having an average roughness Ra of 0.3 μ

m or greater, formed on a surface in the resin sealing region of the lead frame material, and a flat and smooth face, having the average roughness Ra less than that of the roughened face, on a surface outside the resin sealing region of the lead frame material, and

wherein a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, is provided on a whole surface of the lead frame material.

24. The semiconductor device according to claim 23,

wherein the roughened face is formed on a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.

25. A semiconductor device comprising:

a semiconductor chip;

a circuit member including a lead frame material having a die pad onto which the semiconductor chip is mounted, and a lead part electrically connected with the semiconductor chip located on the die pad, the lead frame material being formed from a rolled copper plate or a rolled copper-alloy plate;

a bonding wire electrically connecting the semiconductor chip located on the die pad with the lead part; and

an electrically insulating sealing resin sealing the circuit member, the semiconductor chip and the bonding wire, such that a portion of the lead part of the circuit member can be exposed,

wherein a single plated layer composed of an Ag plated layer, a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, is provided on a surface of the die pad opposed to the semiconductor chip as well as on a portion, connected with the bonding wire, of a surface of the lead part, and

wherein the lead frame material includes a resin sealing region sealed by the sealing resin, together with the semiconductor chip located on the die pad,

wherein the lead frame material includes a roughened face formed on a portion, on which no plated layer is formed, of a surface in the resin sealing region of the lead frame material, the roughened face having an average roughness Ra of 0.3 μ

m or greater, and a flat and smooth face, having the average roughness Ra less than that of the roughened face, on a surface outside the resin sealing region of the lead frame material, and

wherein a solder plated layer is formed on a surface of the exposed portion of the lead part.

26. The semiconductor device according to claim 25,

wherein the plated layer is formed on a top surface of the die pad of the lead frame material as well as on a portion, connected with the bonding wire, of a top surface of the lead part of the lead frame material, and

wherein the roughened face is formed on a portion of a top surface, a side surface and a bottom surface, in the resin sealing region of the lead frame material.