METHOD OF ELIMINATING A LITHOGRAPHY OPERATION

• US 20090146322A1
• Filed: 12/07/2007
• Published: 06/11/2009
• Est. Priority Date: 12/07/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: WELING, MILIND, Sezginer, Abdurrahman
• Granted Patent: US 8,440,569 B2
• Time in Patent Office: Days
• US Class Current: 257/786
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/32139 using masks

Abstract

Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.

Claims

1. A method of semiconductor device fabrication, comprising:

depositing a layer of a first material and patterning the layer to form a first pattern, wherein the first pattern defines wide and narrow space features;

depositing spacer material over the first pattern on the substrate; and

etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space feature defined by the first pattern and remains within narrow a space feature defined by the first pattern.

2. The method of claim 1, further comprising removing the first pattern from the substrate.

3. The method of claim 1, further comprising depositing a layer of the first material over the substrate after the spacer material is etched and polishing the surface.

4. The method of claim 1, wherein spacer material remaining in the narrow space is approximately twice the width of the spacer material remaining adjacent vertical surfaces of the wide space feature.

5. The method of claim 1, wherein the first material comprises polysilicon material.

6. The method of claim 1, wherein the remaining spacer material forms a spacer pattern and further comprising etching the substrate to transfer the spacer pattern to an underlying layer.

7. The method of claim 1, wherein features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.

8. A method of semiconductor device fabrication using spacer double-patterning to create lines and components in the same mask layer, comprising:

depositing a pattern of a first material on a semiconductor substrate, wherein the pattern comprises a line defined by the first material and a space defined by the first material;

depositing second material over the substrate; and

etching the second material such that the second material is partially removed from the substrate, thereby forming a pattern of second material, the pattern of second material comprising a first feature adjacent the line and a second feature within the space.

9. The method of claim 8, wherein the first and second features are for lines and logic device components, respectively, and the first and second features are formed in the second material in the same mask layer.

10. The method of claim 8, wherein the first feature is part of a memory array and the second feature is part of a circuit associated with the memory array.

11. The method of claim 8, wherein the second material in the space is approximately twice the width of the second material adjacent the line.

12. The method of claim 8, wherein the second feature is in a range of from one to two times the width of the first feature.

13. The method of claim 8, wherein depositing comprises physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy or atomic layer deposition.

14. The method of claim 8, wherein the second material comprises silicon nitride, silicon oxide, or silicon oxynitride.

15. The method of claim 8, further comprising etching the remaining second material to trim contact pads or other components created by the remaining second material.

16. A semiconductor device having a plurality of layers, wherein a layer comprises a series of lines and components formed by a spacer double patterning process, the method comprising:

depositing a layer of a first material on a substrate of the semiconductor device and patterning the layer to form a pattern, wherein the pattern comprises an elongated trace defined by the first material and a cavity defined by the first material;

depositing second material over the substrate; and

etching the second material such that the second material is partially removed from the substrate, thereby forming a pattern of second material, the pattern of second material comprising a line adjacent the elongated trace and a component within the cavity.

17. The semiconductor device of claim 16, wherein the line and component are formed in the second material in the same mask layer.

18. The semiconductor device of claim 16, wherein the first feature is part of a memory array and the second feature is part of a circuit associated with the memory array.

19. The semiconductor device of claim 16, wherein the component is approximately twice the width of the line.

20. The semiconductor device of claim 16, wherein the width of the component is in a range of from one to two times the width of the line.

21. A method of producing a dataset for creating a photomask for a layout of a circuit design, comprising:

selecting a first set of data representing line features of the layout;

selecting a second set of data representing device features of the layout that are wider than the lines;

generating a first subset of the data set, wherein the first subset represents a first pattern of alternating spaces on the layout between the lines; and

generating a second subset of the data set, wherein the second subset comprises a second pattern arranged so as to define spaces on the layout that correspond to the device features.

22. The method of claim 21, wherein the line features are part of a memory array and the device features are part of a circuit associated with the memory array.

23. The method of claim 21, wherein the device features are approximately twice the width of the line features.

24. The method of claim 21, wherein the width of the device features is in a range of from one to two times the width of the line features.

25. The method of claim 21, wherein the method is performed by a computer program product embodied on computer usable media.