SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER

• US 20090146701A1
• Filed: 12/02/2008
• Published: 06/11/2009
• Est. Priority Date: 12/07/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: GOMIKAWA, Kenji, NOGUCHI, Mitsuhiro
• Granted Patent: US 7,872,289 B2
• Time in Patent Office: Days
• US Class Current: 327/144
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Claims

1. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region;

MOS transistors each of which is formed on a first one of the element regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on a second one of the element regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to either of the source and the drain of each of the MOS transistors, the voltage generating circuit outputting a voltage from a first one of the MOS transistors in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second one of the MOS transistors in the initial stage in the series connection;

a contact plug which is formed on at least either of the source and the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the contact plug both for the first one of the MOS transistors being larger than that for the second one of the MOS transistors; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit is applied to the memory cell.

2. The device according to claim 1, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the second one of the element regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

3. The device according to claim 1, wherein first one of the element regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

4. The device according to claim 1, further comprising an impurity-doped region which is provided immediately below the element isolation region and has a peak concentration of a p-type impurity of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>,

wherein an interval between one of the element regions and the impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

5. The device according to claim 1, wherein a distance in a gate width direction of the gate between the contact plug for the first one of the MOS transistors and the element isolation region is larger than that between the contact plug for the second one of the MOS transistors and the element isolation region.

6. The device according to claim 1, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in a phase.

7. The device according to claim 1, wherein each of the MOS transistors includes:

a first gate electrode layer which is formed on the first one of the element regions with a first gate insulation film interposed therebetween; and

a second gate electrode layer which is formed on the first gate electrode layer with a first inter-gate insulation film interposed therebetween, the second gate electrode layer being electrically connected to the first gate electrode layer, and

the memory cell includes;

a charge accumulation layer which is formed on a semiconductor substrate with a second gate insulation film interposed therebetween; and

a control gate electrode which is formed on the charge accumulation layer with a second inter-gate insulation film interposed therebetween, the control gate electrode being electrically isolated to the charge accumulation layer.

8. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region;

MOS transistors each of which is formed on a first one of the element regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on a second one of the element regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to either of the source and the drain of each of the MOS transistors, the voltage generating circuit outputting a voltage from a first one of the MOS transistors in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second one of the MOS transistors in the initial stage in the series connection;

a contact plug which is formed on at least either of the source and the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance in a gate width direction of the gate between the contact plug for the first one of the MOS transistors and the element isolation region being larger than that between the contact plug for the second one of the MOS transistors and the element isolation region; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit is applied to the memory cell.

9. The device according to claim 8, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the second one of the element regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

10. The device according to claim 8, wherein first one of the element regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

11. The device according to claim 8, further comprising an impurity-doped region which is provided immediately below the element isolation region and has a peak concentration of a p-type impurity of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>,

wherein an interval between one of the element regions and the impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

12. The device according to claim 8, further comprising an impurity-doped region which is formed immediately below the element isolation region to surround the element regions and has a peak concentration of a p-type impurity of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>,

wherein a distance between one of the element regions for the first one of the MOS transistors and the impurity-doped region is larger than that between one of the element regions for the second one of the MOS transistors and the impurity-doped region.

13. The device according to claim 8, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in a phase.

14. The device according to claim 8, wherein each of the MOS transistors includes:

a first gate electrode layer which is formed on the first one of the element regions with a first gate insulation film interposed therebetween; and

a second gate electrode layer which is formed on the first gate electrode layer with a first inter-gate insulation film interposed therebetween, the second gate electrode layer being electrically connected to the first gate electrode layer, and

the memory cell includes;

a charge accumulation layer which is formed on a semiconductor substrate with a second gate insulation film interposed therebetween; and

a control gate electrode which is formed on the charge accumulation layer with a second inter-gate insulation film interposed therebetween, the control gate electrode being electrically isolated to the charge accumulation layer.

15. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region;

an impurity-doped region which is formed immediately below the element isolation region and surrounds the element regions;

MOS transistors each of which is formed on a first one of the element regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on a second one of the element regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to either of the source and the drain of each of the MOS transistors, the voltage generating circuit outputting a voltage from a first one of the MOS transistors in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second one of the MOS transistors in the initial stage in the series connection, a distance between one of the element regions for the first one of the MOS transistors and the impurity-doped region being larger than that between one of the element regions for the second one of the MOS transistors and the impurity-doped region; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit is applied to the memory cell.

16. The device according to claim 15, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the second one of the element regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

17. The device according to claim 15, wherein first one of the element regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

18. The device according to claim 15, wherein the impurity-doped region contains p-type impurity,

the p-type impurity has a peak concentration of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>, and

an interval between one of the element regions and the impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

19. The device according to claim 15, further comprising a contact plug which is formed on at least either of the source and the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements,

wherein a distance between the gate and the contact plug for the first one of the MOS transistors is larger than that for the second one of the MOS transistors.

20. The device according to claim 15, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in a phase.