AUTOMATIC ACTIVITY DETECTION IN A DISPLAY CONTROLLER

• US 20090146979A1
• Filed: 12/08/2008
• Published: 06/11/2009
• Est. Priority Date: 10/18/2004
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Inventors: KEENE, David, CHILUKURI, Ram, LATTANZI, John, NOORBAKHSH, Ali
• Granted Patent: US 8,766,956 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (T_CLK) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active

Claims

1. In a display controller having an on-board power supply and a reference clock signal generator circuit arranged to generate a reference clock signal (T_CLK), a method of detecting when the on-board power supply is powered on or off by an auto activity detection circuit, comprising:

determining if the reference clock signal (T_CLK) is toggling;

if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal; and

outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active.

2. In a display controller having an on-board power supply and a reference clock signal generator circuit arranged to generate a reference clock signal (T_CLK), an auto activity detection circuit, comprising:

an input node coupled to the reference clock signal generator circuit;

a first resistor having a first resistor first terminal connected to the input node and a first resistor second terminal;

a capacitor having a capacitor first terminal connected to the first resistor second terminal at a node N and a capacitor second terminal;

a second resistor having a second resistor first terminal connected to the capacitor second terminal and a second resistor second terminal connected to the node N; and

an output node coupled to the node N1, wherein when the reference clock signal generator circuit is generating the reference clock signal (T_CLK), the capacitor charges the node N1 to a high voltage that, in turn, drives the output node to HIGH indicating that the reference clock generator circuit is in fact generating the reference clock signal (T_CLK).

3. The circuit as recited in claim 2, further comprising:

a first inverter having an input coupled to the node N and a first inverter output; and

a second inverter having a second inverter input coupled in series with the first inverter output and a second inverter output coupled to a node N2.

4. The circuit as recited in claim 3, further comprising:

a NAND gate having a first input coupled to the node N2 and a second input coupled to an I_CORE detect signal generator;

a third inverter having a first input coupled to the output of the NAND gate;

a NOR gate having a first input coupled to an output of the third inverter and a second input coupled to an iEDID_EN_PAD enable signal generator; and

a fourth inverter having an input coupled to a NAND gate output and an output coupled to the output node, wherein when the node N1 goes HIGH, the node N2, in turn, goes HIGH and if the iCORE_DETECT is set to HIGH, then the node N3 will be HIGH resulting in an output ACT signal to be HIGH indicating that the controller power is on.

5. The circuit as recited in claim 4, wherein the output ACT signal can also be set to ONE by way of the iEDID_EN_PAD enable signal (which is a bond option signal).

6. In a display controller having an on-board power supply and a reference clock signal generator circuit having an input node arranged to generate a reference clock signal (T_CLK), a method of detecting when the on-board power supply is powered on or off, comprising:

connecting a first resistor having a first resistor first terminal to the input node and a first resistor second terminal;

connecting a capacitor having a capacitor first terminal to the first resistor second terminal at a node N and a capacitor second terminal;

connecting a second resistor having a second resistor first terminal to the capacitor second terminal;

connecting a second resistor second terminal to the node N; and

connecting an output node coupled to the node N, wherein when the reference clock signal generator circuit is generating the reference clock signal (T_CLK), the capacitor charges the node N to a high voltage that, in turn, drives the output node to HIGH indicating that the reference clock generator circuit is generating the reference clock signal (T_CLK).

7. The method as recited in claim 6, further comprising:

connecting a first inverter having an input to the node N and a first inverter output; and

connecting a second inverter having a second inverter input in series with the first inverter output and a second inverter output coupled to a node N2.

8. The method as recited in claim 7, further comprising:

connecting a NAND gate having a first input to the node N2 and a second input;

connecting the second input to an CLK detect signal generator;

connecting a third inverter having a first input to the output of the NAND gate;

connecting a NOR gate having a first input to an output of the third inverter

connecting a second input to an enable signal generator; and

connecting a fourth inverter having an input to a NAND gate output and an output coupled to the output node, wherein when the node N goes HIGH, the node N2, in turn, goes HIGH and if the CLK detect signal is set to HIGH, then the node N3 will be HIGH resulting in an output ACT signal to be HIGH indicating that the controller power is on.

9. The circuit as recited in claim 8, wherein the output ACT signal can also be set to ONE by way of the enable signal.