NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES

• US 20090147579A1
• Filed: 11/20/2008
• Published: 06/11/2009
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, Khan, Sakhawat M.
• Granted Patent: US 7,848,159 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Claims

1-88. -88. (canceled)

89. A method comprising:

reading a fuse non-volatile memory location for configuration data in response to a page read command;

storing said configuration data in a volatile memory location; and

using the configuration data to initiate a page read sequence for a memory.

127. The method of claim 89 further comprising autozeroing an input and output in order to zero out offset in an amplifier.

128. The method of claim 89 further comprising autozeroing an input and output in order to zero out offset in a reference sense amplifier.

129. The method of claim 128 further comprising capacitively sensing an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

130. The method of claim 128 further comprising selectively coupling the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

131. The method of claim 89 further comprising autozeroing an input and output in order to zero out offset of reference sense circuitry.

132. The method of claim 89 further comprising coupling inputs of a reference sense amplifier to an output signal in response to an autozero signal.

133. The method of claim 89 further comprising:

operatively coupling a reference array to reference memory subarrays; and

providing stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

134. The method of claim 89 further comprising setting an input and an output of reference circuitry in response to an autozero signal.

135. The method of claim 89 further comprising autozeroing an input and an output in order to zero out an offset of reference circuitry.

136. The method of claim 127 further comprising coupling inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal.

155. The method of claim 89 further comprising executing a configuration (fuse) bit initialization that loads data from fuse memory cells to volatile latches in a fuse circuit block.

156. The method of claim 89 further comprising:

placing all data cells in an addressed page into voltage-mode read states;

reading cell (reference and data) voltages for the data cells; and

comparing read verify voltages with cell read back voltages to determine whether to continue the page read sequence.

157. The method of claim 89 further comprising:

applying an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

158. The method of claim 157 wherein erase blocks include a plurality of pages of memory cells.

159. The method of claim 157 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

163. The method of claim 89 further comprising:

applying a read algorithm programmed via fuses upon one selected page of memory cells at a time.

164. The method of claim 163 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.

90. A method comprising:

reading a fuse non-volatile memory location for configuration data in response to a page program command;

storing said configuration data in a volatile memory location; and

using the configuration data to initiate a page programming sequence for a memory.

137. The method of claim 90 further comprising autozeroing an input and output in order to zero out offset in an amplifier.

138. The method of claim 90 further comprising autozeroing an input and output in order to zero out offset in a reference sense amplifier.

139. The method of claim 138 further comprising capacitively sensing an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

140. The method of claim 138 further comprising selectively coupling the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

141. The method of claim 90 further comprising autozeroing an input and output in order to zero out offset of reference sense circuitry.

142. The method of claim 90 further comprising coupling inputs of a reference sense amplifier to an output signal in response to an autozero signal.

143. The method of claim 90 further comprising:

operatively coupling a reference array to reference memory subarrays; and

providing stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

144. The method of claim 90 further comprising setting an input and an output of reference circuitry in response to an autozero signal.

145. The method of claim 90 further comprising autozeroing an input and an output in order to zero out an offset of reference circuitry.

147. The method of claim 90 further comprising executing a configuration (fuse) bit initialization that loads data from fuse memory cells to volatile latches in a fuse circuit block.

148. The method of claim 90 further comprising comparing program verify voltages of cells against data cell read back voltages to indicate whether further programming is required.

149. The method of claim 90 further comprising performing the page programming sequence including an iterative verify-program loop, wherein the iterative verify-program loop ends the page programming sequence if a program pulse count reaches a maximum value.

150. The method of claim 149 wherein the iterative verify-program loop determines how many cells have been placed in a program inhibit mode, and further comprising continuing the page programming sequence once the iterative verify-program loop determines that all of the cells have been placed in the program inhibit mode.

151. The method of claim 90 further comprising:

performing the page programming sequence including an iterative verify-program loop, wherein the iterative verify-program loop determines how many cells have been placed in a program inhibit mode; and

continuing the page programming sequence once the iterative verify-program loop determines that all of the cells have been placed in the program inhibit mode.

152. The method of claim 90 further comprising:

generating upper program margin verify voltages; and

comparing the upper program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

153. The method of claim 152 further comprising:

generating lower program margin verify voltages; and

comparing the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

154. The method of claim 90 further comprising:

generating lower program margin verify voltages; and

comparing the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

160. The method of claim 90 further comprising:

applying an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

161. The method of claim 160 wherein erase blocks include a plurality of pages of memory cells.

162. The method of claim 160 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

165. The method of claim 90 further comprising:

applying a read algorithm programmed via fuses upon one selected page of memory cells at a time.

166. The method of claim 165 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.

91-126. -126. (canceled)

146. The method of 90 further comprising:

coupling a reference array to reference memory subarrays; and

providing stored reference signals used for programming reference memory cells, the stored reference signals corresponding to detected reference signals.