MEMORY REFRESH METHOD AND APPARATUS

• US 20090147606A1
• Filed: 12/05/2007
• Published: 06/11/2009
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda North America Corporation (Infineon Technologies AG)
• Inventors: Daniel, Alan
• Granted Patent: US 7,551,505 B1
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

Claims

1. In an integrated circuit having rows of memory cells selectable through a row address, a method of selectively refreshing the rows comprising:

monitoring row address activity to identify which bits of the row address change state at least once during a memory access operation; and

skipping refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

2. The method of claim 1, further comprising determining a refresh clock frequency based on which row address bits do not change state at least once during the memory access operation.

3. The method of claim 1, further comprising determining a refresh period based on which row address bits do not change state at least once during the memory access operation.

4. The method of claim 1, wherein monitoring row address activity to identify which bits of the row address change state at least once during the memory access operation comprises triggering individual bits of a control signal based on which row address bits change state at least once when the integrated circuit is active.

5. The method of claim 4, wherein skipping refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation comprises activating the row address bits associated with each triggered bit of the control signal during a refresh cycle while maintaining the remaining row address bits in a constant logic state.

6. The method of claim 4, further comprising determining a refresh clock frequency based on the number of triggered control signal bits.

7. The method of claim 4, further comprising determining a refresh period based on the number of triggered control signal bits.

8. An integrated circuit, comprising:

one or more memory array segments configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and

a refresh controller configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

9. The integrated circuit of claim 8, wherein the refresh controller is further configured to determine a refresh clock frequency based on which row address bits do not change state at least once during the memory access operation.

10. The integrated circuit of claim 8, wherein the refresh controller is further configured to determine a refresh period based on which row address bits do not change state at least once during the memory access operation.

11. The integrated circuit of claim 8, wherein the refresh controller is configured to trigger individual bits of a control signal based on which row address bits change state at least once when the integrated circuit is active.

12. The integrated circuit of claim 11, wherein the refresh controller is configured to activate the row address bits associated with each triggered bit of the control signal during a refresh cycle while maintaining the remaining row address bits in a constant logic state.

13. The integrated circuit of claim 11, wherein the refresh controller is further configured to determine a refresh clock frequency based on the number of triggered control signal bits.

14. The integrated circuit of claim 11, wherein the refresh controller is further configured to determine a refresh period based on the number of triggered control signal bits.

15. In an integrated circuit having rows of memory cells selectable through a row address, a method of selectively refreshing the rows comprising:

identifying one or more bits of the row address which do not change state at least once when the integrated circuit is active;

skipping refresh of the rows selectable through the identified row address bits; and

determining a refresh clock frequency based on how many row address bits are identified.

16. The method of claim 15, wherein identifying one or more bits of the row address which do not change state at least once when the integrated circuit is active comprises triggering individual bits of a control signal based on which row address bits change state at least once when the integrated circuit is active.

17. The method of claim 16, wherein skipping refresh of the rows selectable through the identified row address bits comprises activating the row address bits associated with each triggered bit of the control signal during a refresh cycle while maintaining the remaining row address bits in a constant logic state.

18. The method of claim 16, wherein determining the refresh clock frequency comprises determining the refresh clock frequency based on the number of triggered control signal bits.

19. An integrated circuit, comprising:

one or more memory array segments configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and

a refresh controller configured to identify one or more bits of the row address which do not change state at least once when the integrated circuit is active, to skip refresh of the rows selectable through the identified row address bits, and to determine a refresh clock frequency based on how many row address bits are identified.

20. The integrated circuit of claim 19, wherein the refresh controller is configured to trigger individual bits of a control signal based on which row address bits change state at least once when the integrated circuit is active.

21. The integrated circuit of claim 20, wherein the refresh controller is configured to activate the row address bits associated with each triggered bit of the control signal during a refresh cycle while maintaining the remaining row address bits in a constant logic state.

22. The integrated circuit of claim 20, wherein the refresh controller is configured to determine the refresh clock frequency based on the number of triggered control signal bits.

23. A system, comprising:

a controller;

one or more memory array segments coupled to the controller and configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and

a refresh controller configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

24. The system of claim 23, wherein the refresh controller is further configured to determine a refresh clock frequency based on which row address bits do not change state at least once during the memory access operation.

25. The system of claim 24, wherein the refresh controller is further configured to determine a refresh period based on which row address bits do not change state at least once during the memory access operation.