SYSTEM FOR TESTING THE UPSTREAM CHANNEL OF A CABLE NETWORK

• US 20090147671A1
• Filed: 02/13/2009
• Published: 06/11/2009
• Est. Priority Date: 11/01/2000
• Status: Active Grant

• Current Assignee: VeEX Incorporated
• Original Assignee: Sunrise Telecom Incorporated
• Inventors: Barker, James E., Richards, Robert L., Jaworski, Richard C., Elliott, Herman B.
• Granted Patent: US 7,721,162 B2
• Time in Patent Office: Days
• US Class Current: 370/216
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A system for testing a portion of a cable network provides a pattern generator, Addresser, forward error corrector, and comparator. The system is particularly adapted to testing the upstream channel in a cable network. The pattern generator generates a test signal. The addresser addresses the signal to a known server and also instructs the known server to return the test signal to the test system. The forward error corrector corrects errors introduced in the test signal in transmission from the known server to the test system. The comparator then compares the returned test signal to the originally transmitted test signal to determine the performance of the back channel. Preferably, the comparator uses a bit error rate test to determine the performance of the back channel.

Claims

1. A system for determining the performance of a portion of a network, the system comprising:

a receiver including circuitry for;

receiving a signal from a transmission point at a destination, and

returning the signal to the transmission point; and

a transmitter including circuitry for;

transmitting the signal from the transmission point onto the portion of the network,

correcting errors introduced into the signal in transmission from the destination to the transmission point, and

determining the performance of the portion of the network from the transmission point to the destination.

2. The system of claim 1 wherein the transmitter includes further circuitry for determining the performance of the portion of the network using the corrected signal.

3. The system of claim 1 wherein the transmitter includes further circuitry for forward error correction.

4. The system of claim 3 wherein the further circuitry further comprises additional circuitry for:

determining residual errors in portions of the signal received at the transmission point; and

discarding the portions of the signal that contain residual errors.

5. The system of claim 3 wherein the further circuitry further comprises additional circuitry for comparing the signals tests for bit error rate, block error rate, or a combination thereof.

6. A system for determining the performance of a portion of a network, the method comprising:

a receiver including circuitry for;

receiving a signal at a destination, and

returning the non-discarded signal portions to a transmission point; and

a transmitter including circuitry for;

transmitting a signal from a transmission point onto the portion of the network, detecting errors in the signal received at the destination,

discarding portions of the signal received at the destination that contain errors,

determining the magnitude of the discarded portions of the signal from the returned, non-discarded portions,

using a block error rate test to determine the performance of the portion of the network, and

determining the performance of the portion of the network from the transmission point to the destination.

7. The system of claim 6 wherein the network is a cable network.

8. The system of claim 6 wherein the portion of the cable network is a local area cable loop.

9. The system of claim 8 wherein the transmitter includes further circuitry for determining the performance of an upstream channel of the local area cable loop.

10. The system of claim 9 wherein the transmitter includes additional circuitry for transmitting the signal in the upstream channel.

11. The system of claim 9 wherein the signal is returned in a forward channel of the local area cable loop.

12. The system of claim 6 wherein the destination is a cable modem termination system.

13. The system of claim 6 wherein the transmitter includes further circuitry for using forward error correction.

14. The system of claim 6 wherein the transmitter includes further circuitry for displaying the performance.

15. A device for determining the performance of a portion of a network comprising:

a forward error corrector; and

a comparator coupled to the forward error corrector.

16. The device of claim 15 further comprising a pattern generator.

17. The device of claim 15 wherein the network is a cable network.

18. The device of claim 17 wherein the portion of the cable network is a local area cable loop.

19. The device of claim 18 wherein the device is coupled to an upstream channel of the local area cable loop.

20. The device of claim 19 wherein the device is also coupled to a forward channel of the local area cable loop.

21. The device of claim 15 further comprising an addresser.

22. The device of claim 19 further comprising an addresser.

23. The device of claim 15 further comprising:

a pattern generator coupled to the comparator; and

an addresser coupled to the pattern generator.

24. The device of claim 17 further comprising a cable modem termination system.

25. The device of claim 23 wherein:

the network is a cable network;

the portion of the network is a local area cable loop; and

the addresser is coupled to an upstream channel of the local area cable loop.

26. A device for determining the performance of a portion of a network comprising:

circuitry for correcting errors in a signal; and

circuitry for comparing a signal to a standard.

27. The device of claim 26 further comprising circuitry for generating the standard.

28. The device of claim 26 wherein the network is a cable network.

29. The device of claim 28 wherein the portion of the cable network is a local area cable loop.

30. The device of claim 26 further comprising means for addressing a signal to a destination.

31. The device of claim 30 wherein the destination is a cable modem termination system.

32. A memory device for storing program instructions comprising:

a forward error corrector; and

a comparator.

33. The memory device of claim 32 further comprising program instructions for a pattern generator.

34. The memory device of claim 33 further comprising program instructions for an addresser.

35. The memory device of claim 32 further comprising program instructions for an addresser.

36. A system for determining the performance of a portion of a network, the system comprising:

a cable modem termination system (CMTS) for;

receiving a test packet, and

returning the test packet from the CMTS on a downstream portion of the network; and

a tester for;

transmitting a test packet from onto an upstream portion of the network, and

using the test packet in the tester to determine the performance of the upstream portion of the network.

37. The system of claim 36 wherein the tester includes circuitry for:

transmitting a plurality of test packets from the tester onto the upstream portion of the network; and

using all of the plurality of test packets to determine the performance of the upstream portion of the network.

38. The system of claim 36 wherein the tester includes circuitry for:

transmitting a plurality of test packets from the tester onto the upstream portion of the network; and

discarding test packets with errors by the CMTS.

39. The system of claim 36 wherein the performance is measured as a block error rate.

40. The system of claim 36 wherein the performance is measured as a bit error rate.

41. The system in claim 36 where the performance is measured as a function of discarded packets.

42. The system in claim 36 wherein the network is a cable network.

43. The system in claim 36 wherein the tester includes circuitry for:

transmitting the test packet in the upstream channel of a cable network; and

returning the test packet in the forward channel of a cable network.

44. The system in claim 36 wherein the tester includes circuitry for:

transmitting the test packet in the upstream channel of an Internet network; and

returning the test packet in the forward channel of an Internet.

45. The system in claim 36 wherein transmitting the test packet transmits a test packet containing information related to the test packet used by the tester to determine the performance.

46. The system of claim 36 wherein the method repeats.

47. The system in claim 36 wherein wherein the tester includes circuitry for:

transmitting a plurality of test packets from the tester onto the upstream portion of the network; and

transmitting the plurality of test packets transmits the plurality of test packets containing a pattern that repeats in each of the plurality of test packets.

48. The system in claim 36 wherein the tester includes circuitry for:

transmitting a plurality of test packets from the tester onto the upstream portion of the network; and

transmitting the plurality of test packets transmits the plurality of test packets with information identifying each of the plurality of test packets as a test packet.

49. The system in claim 36 wherein the tester includes circuitry for:

transmitting a plurality of test packets from the tester onto the upstream portion of the network;

returning the plurality of test packets from the CMTS to the tester on the downstream portion of the network; and

ignoring an error in a test packet of the plurality of test packets from the CMTS.

50. The system in claim 36 wherein the tester includes circuitry for transmitting information of the performance to a computer for monitoring the network.

51. The system in claim 36 wherein the tester includes circuitry for monitoring a cable modem using a computer.

52. The system in claim 36 wherein the tester includes circuitry for monitoring performance using a computer.