STRUCTURE FOR HANDLING DATA REQUESTS

• US 20090150572A1
• Filed: 05/04/2008
• Published: 06/11/2009
• Est. Priority Date: 12/10/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: ALLEN, JAMES J. JR., Trombley, Michael R., Jenkins, Steven K., Mossman, James A.
• Granted Patent: US 7,937,533 B2
• Time in Patent Office: Days
• US Class Current: 710/15
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/507 using speculative control

Abstract

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

Claims

1. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

a computer system comprising

a CPU;

a memory controller;

memory;

a bus connecting the CPU, memory controller and memory;

circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued; and

circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

2. The design structure of claim 1, further comprising:

circuitry for monitoring a selected computer system state; and

circuitry for dynamically adjusting the speculative read threshold based on the selected computer system state.

3. The design structure of claim 2, further comprising circuitry for preventing a read request from dispatching as a speculative read request if the percentage of current memory controller resources being used for speculative reads is equal to or greater than the speculative read threshold.

4. The design structure of claim 3, further comprising circuitry for preventing the read from dispatching as a speculative read if the memory controller is full.

5. The design structure of claim 4, further comprising circuitry for determining the speculative read threshold based on a system read request rate.

6. The design structure of claim 5, further comprising circuitry for determining the speculative read threshold based on a percentage of read requests that pass coherency checking and require data from the memory controller.

7. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the computer system.

8. The design structure of claim 1, wherein the design structure resides on the machine readable storage medium as a data format used for the exchange of layout data of integrated circuits.