Processing Unit Incorporating Vectorizable Execution Unit

• US 20090150647A1
• Filed: 12/07/2007
• Published: 06/11/2009
• Est. Priority Date: 12/07/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam James, Mejdrich, Eric Oliver, Tubbs, Matthew Ray
• Granted Patent: US 7,809,925 B2
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical execution units in different modes. By doing so, processing lanes can be selectively grouped together to operate as different types of vector execution units and/or scalar execution units, and if desired, dynamically switched during runtime to process various types of instruction streams in a manner that is best suited for each type of instruction stream. As a consequence, a single vectorizable execution unit may be configurable, e.g., via software control, to operate either as a vector execution or a plurality of scalar execution units.

Claims

1. A circuit arrangement, comprising:

a vectorizable floating point unit including a plurality of processing lanes; and

control logic coupled to the vectorizable floating point unit and configured to selectively operate the vectorizable floating point unit in vector and scalar modes, wherein in the vector mode, the control logic is configured to operate the plurality of processing lanes collectively as a single instruction multiple data (SIMD) execution unit, and in the scalar mode, the control logic is configured to operate the plurality of processing lanes as separate scalar execution units.

13. An integrated circuit device including the circuit arrangement of claim 1.

14. A program product comprising a computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 1.

2. A circuit arrangement, comprising:

a vectorizable execution unit including a plurality of processing lanes, wherein the plurality of processing lanes includes at least first and second processing lanes; and

control logic coupled to the vectorizable execution unit and configured to selectively operate the vectorizable execution unit in first and second modes, wherein in the first mode, the control logic is configured to organize the first and second processing lanes into the same logical execution unit such that the first and second processing lanes operate collectively as a vector execution unit, and in the second mode, the control logic is configured to organize the first and second processing lanes into separate logical execution units such that the first and second processing lanes operate independently and in parallel with one another.

3. The circuit arrangement of claim 2, wherein the control logic is configured to, in the second mode, operate the first and second processing lanes as separate scalar execution units.

4. The circuit arrangement of claim 3, wherein the plurality of processing lanes further includes third and fourth processing lanes, wherein the control logic is configured to, in the first mode, organize the first, second, third and fourth processing lanes into the same logical execution unit such that the first, second, third and fourth processing lanes operate collectively as a vector execution unit, and in the second mode, organize the first and third processing lanes into a first logical execution unit and organize the second and fourth processing lanes into a second logical execution unit that is different from the first logical execution unit such that the first and second logical execution units operate as independent and parallel vector execution units.

5. The circuit arrangement of claim 2, wherein the control logic includes issue logic configured to receive instructions from a plurality of threads, the issue logic configured to, in the first mode, issue a single instruction multiple data (SIMD) instruction to the vectorizable execution unit for collective processing by the first and second processing lanes.

6. The circuit arrangement of claim 5, wherein the issue logic is further configured to, in the second mode, issue first and second instructions in parallel to the vectorizable execution unit for independent and parallel execution by the first and second processing lanes.

7. The circuit arrangement of claim 6, wherein the plurality of threads includes first and second threads, and wherein the issue logic further includes:

issue select logic configured to schedule issuance of instructions from the first and second threads; and

multiplexing logic coupled to the issue select logic and configured to, in the first mode, route instructions issued by the issue select logic to the vectorizable execution unit for collective processing by the first and second processing lanes, and in the second mode, bypass the issue select logic such that instructions received from the first thread are routed to the first processing lane and instructions from the second thread are routed to the second processing lane for parallel execution of instructions from the first and second threads in the first and second processing lanes, respectively.

8. The circuit arrangement of claim 2, further comprising a register file coupled to the vectorizable execution unit, wherein in the first mode, the register file is partitioned into a first plurality of registers, and in the second mode, the register file is partitioned into a second plurality of registers that is different from the first plurality of registers.

9. The circuit arrangement of claim 8, wherein the control logic is configured to cause the register file to be flushed in response to a mode switch between the first and second modes.

10. The circuit arrangement of claim 2, further comprising a mode register configured to be written to by software to switch between the first and second modes.

11. The circuit arrangement of claim 2, wherein the control logic is further configured to selectively operate the vectorizable execution unit in a third mode that organizes the first and second processing lanes into different logical execution units from the logical execution units defined in the first and second modes.

12. The circuit arrangement of claim 2, wherein the plurality of processing lanes further includes third and fourth processing lanes, wherein the control logic includes issue logic configured to receive instructions from first, second, third and fourth threads, wherein the first, second, third and fourth processing lanes are respectively associated with the first, second, third and fourth threads, wherein the issue logic is configured to, in the first mode, schedule issuance of single instruction multiple data (SIMD) instructions received from the first, second, third and fourth threads to the vectorizable execution unit for collective processing by the first, second, third and fourth processing lanes, and in the second mode, route scalar instructions from the first, second, third and fourth threads to the associated first, second, third and fourth processing lanes for parallel execution of the scalar instructions by the first, second, third and fourth processing lanes, and wherein the circuit arrangement further comprises a register file coupled to the vectorizable execution unit, wherein in the first mode, the register file is partitioned into four word registers, and in the second mode, the register file is partitioned into single word registers.

15. A method of operating a vectorizable execution unit, the method comprising:

operating the vectorizable execution unit in a first mode such that first and second processing lanes among a plurality of processing lanes in the vectorizable execution unit are organized into the same logical execution unit and operate collectively as a vector execution unit;

switching the vectorizable execution unit from the first mode to a second mode after operating the vectorizable execution unit in the first mode; and

after switching the vectorizable execution unit from the first mode to the second mode, operating the vectorizable execution unit in the second mode such that the first and second processing lanes are organized into separate logical execution units and operate independently and in parallel with one another.

16. The method of claim 15, further comprising, when the vectorizable execution unit is in the second mode, operating the first and second processing lanes as separate scalar execution units.

17. The method of claim 16, wherein the plurality of processing lanes further includes third and fourth processing lanes, wherein operating the vectorizable execution unit in the first mode includes organizing the first, second, third and fourth processing lanes into the same logical execution unit such that the first, second, third and fourth processing lanes operate collectively as a vector execution unit, and wherein operating the vectorizable execution unit in the second mode includes organizing the first and third processing lanes into a first logical execution unit and organizing the second and fourth processing lanes into a second logical execution unit that is different from the first logical execution unit such that the first and second logical execution units operate as independent and parallel vector execution units.

18. The method of claim 15, further comprising:

receiving instructions from a plurality of threads; and

in the first mode, issuing a single instruction multiple data (SIMD) instruction received from one of the plurality of threads to the vectorizable execution unit for collective processing by the first and second processing lanes.

19. The method of claim 18, further comprising, in the second mode, issuing first and second instructions in parallel to the vectorizable execution unit for independent and parallel execution by the first and second processing lanes.

20. The method of claim 19, wherein the plurality of threads includes first and second threads, the method further comprising:

using issue select logic to schedule issuance of instructions from the first and second threads; and

selectively bypassing the issue select logic using multiplexing logic such that in the first mode, instructions issued by the issue select logic are routed to the vectorizable execution unit for collective processing by the first and second processing lanes, and in the second mode, the issue select logic is bypassed such that instructions received from the first thread are routed to the first processing lane and instructions from the second thread are routed to the second processing lane for parallel execution of instructions from the first and second threads in the first and second processing lanes, respectively.

21. The method of claim 15, further comprising, in association with switching from the first mode to the second mode, repartitioning a register file in the vectorizable execution unit from a first plurality of registers associated with the first mode to a second plurality of registers that is associated with the second mode and that is different from the first plurality of registers.

22. The method of claim 21, further comprising flushing the register file in association with switching between the first and second modes.

23. The method of claim 15, wherein switching from the first mode to the second mode is performed responsive to a value written to a mode register by software.

24. The method of claim 15, further comprising selectively operating the vectorizable execution unit in a third mode that organizes the first and second processing lanes into different logical execution units from the logical execution units defined in the first and second modes.

25. The method of claim 15, wherein the plurality of processing lanes further includes third and fourth processing lanes, the method further comprising:

receiving instructions from a plurality of threads including first, second, third and fourth threads that are respectively associated with the first, second, third and fourth processing lanes;

in the first mode, scheduling issuance of single instruction multiple data (SIMD) instructions received from the first, second, third and fourth threads to the vectorizable execution unit for collective processing by the first, second, third and fourth processing lanes;

in the second mode, routing scalar instructions from the first, second, third and fourth threads to the associated first, second, third and fourth processing lanes for parallel execution of the scalar instructions by the first, second, third and fourth processing lanes.