Reducing Aging Effect On Registers

• US 20090150656A1
• Filed: 11/03/2006
• Published: 06/11/2009
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gonzalez, Antonio, Vera, Xavier, Abella, Jaume
• Granted Patent: US 8,578,137 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.

Claims

1. A processor comprising:

a storage unit to store data;

a counter to store a first value to indicate how long a portion of the storage unit has maintained an inverted versus a non-inverted value; and

a first logic to cause storage of a second value in the storage unit in response to a detection that the storage unit is to be unused.

2. The processor of claim 1, wherein the first logic causes storage of the second value in the storage unit in response to the first value indicating that the portion of the storage unit has maintained an inverted value for a shorter time period than a non-inverted value.

3. The processor of claim 1, further comprising a second logic to update the second value on a periodic basis.

4. The processor of claim 1, wherein the storage unit comprises a register.

5. The processor of claim 4, further comprising a register file that comprises the register.

6. The processor of claim 5, further comprising a second logic to update the second value based on a value written to one of a plurality of registers in the register file.

7. The processor of claim 4, wherein the detection is in response to an indication that the register is to be released.

8. The processor of claim 1, further comprising a second logic to update the first value based on one or more accesses to the storage unit.

9. The processor of claim 1, wherein the storage unit comprises a plurality of bit cells and each bit cell of the storage unit comprises at least two transistors to store a bit of the data.

10. The processor of claim 1, wherein the storage unit comprises a static random access memory (SRAM) device.

11. The processor of claim 1, further comprising one or more processor cores, wherein at least one of the processor cores comprises the logic.

12. A method comprising:

detecting whether a register is released; and

storing a value in the register based on how long the register has stored an inverted value and a non-inverted value.

13. The method of claim 12, further comprising updating the value after determining that the register has stored an inverted value for a shorter time period than a non-inverted value.

14. The method of claim 12, further comprising updating the value on a periodic basis.

15. The method of claim 12, further comprising updating the value based on a value written to one of a plurality of registers in a register file.

16. The method of claim 12, wherein the storing is performed in response to a determination that a write port is available to write the value into the register.

17. A computing system comprising:

a memory to store data; and

a processor core comprising;

a register to store a portion of the data stored in the memory; and

logic to cause storage of a value in the register in response to a detection that the register is to be released.

18. The system of claim 17, wherein the memory comprises a cache.

19. The system of claim 17, wherein the register comprises a plurality of p-channel metal-oxide semiconductor (P-MOS) or n-channel metal-oxide semiconductor (N-MOS) transistors.

20. The system of claim 17, further comprising logic to update the value based on a value written to one of a plurality of registers in a register file, wherein the register file comprises the register.

21. The system of claim 17, further comprising logic to update the value on a periodic basis.

22. The system of claim 17, further comprising a plurality of processor cores to access the data stored in the memory.

23. The system of claim 17, further comprising an audio device.

24. An apparatus comprising:

a first logic to invert values stored in a first register when the first register is not storing data to be used by a second logic; and

a second register to store inverted values to be stored in the first register.

25. The apparatus of claim 24, wherein the first logic is to invert the values stored in the first register according to a first inversion period.

26. The apparatus of claim 25, wherein the inverted values are to be stored in the first register only if a write port to the first register is available.

27. The apparatus of claim 25, wherein the second logic includes a processor execution unit.

28. The apparatus of claim 27, wherein the first inversion period corresponds to 50% of the processor execution unit'"'"'s operation time.

29. The apparatus of claim 25, wherein the first logic includes an inversion logic and an inversion value update logic.

30. The apparatus of claim 25, wherein the first inversion period is to be measured by a first inversion counter coupled to the first register.