Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Modified Latch Bank
First Claim
1. A data transmission interface comprising:
- a master data latch for receiving and outputting a first transmit data;
a first clock splitter coupled to the master data latch, wherein the first clock splitter supplies a first clock signal to the master data latch;
a first transmission gate coupled to the master data latch and the first clock splitter, wherein the first transmission gate receives a second clock signal from the first clock splitter and receives the first transmit data from an output of the master data latch;
a second clock splitter;
a second transmission gate coupled to the second clock splitter, wherein the second transmission gate receives a third clock signal from the second clock splitter; and
a transmission node coupled to an output of the first transmission gate and an output of the second transmission gate.
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Accused Products
Abstract
A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed.
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Citations
20 Claims
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1. A data transmission interface comprising:
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a master data latch for receiving and outputting a first transmit data; a first clock splitter coupled to the master data latch, wherein the first clock splitter supplies a first clock signal to the master data latch; a first transmission gate coupled to the master data latch and the first clock splitter, wherein the first transmission gate receives a second clock signal from the first clock splitter and receives the first transmit data from an output of the master data latch; a second clock splitter; a second transmission gate coupled to the second clock splitter, wherein the second transmission gate receives a third clock signal from the second clock splitter; and a transmission node coupled to an output of the first transmission gate and an output of the second transmission gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of transmitting data between a source clock domain and a destination clock domain, the method comprising:
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supplying a first transmit data to a master data latch; supplying a first clock enable signal to a first clock splitter; supplying a second clock enable signal to a second clock splitter; supplying a first clock signal to the master data latch from the first clock splitter; supplying a second clock signal to a first transmission gate from the first clock splitter; supplying a third clock signal to a second transmission gate from the second clock splitter; and supplying a second transmit data to the second transmission gate; wherein; the second clock signal and third clock signal are logically mutually exclusive; and the output of the first transmission gate and the output of a second transmission gate are connected to a transmission node. - View Dependent Claims (18, 19, 20)
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Specification