Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Modified Latch Bank

• US 20090150709A1
• Filed: 12/05/2007
• Published: 06/11/2009
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bowers, Benjamin John, Steinmetz, Paul Michael, Arnold, Nicole Marie, Baker, Matthew Wayne, Correale, Anthony JR.
• Granted Patent: US 7,882,385 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed.

Claims

1. A data transmission interface comprising:

a master data latch for receiving and outputting a first transmit data;

a first clock splitter coupled to the master data latch, wherein the first clock splitter supplies a first clock signal to the master data latch;

a first transmission gate coupled to the master data latch and the first clock splitter, wherein the first transmission gate receives a second clock signal from the first clock splitter and receives the first transmit data from an output of the master data latch;

a second clock splitter;

a second transmission gate coupled to the second clock splitter, wherein the second transmission gate receives a third clock signal from the second clock splitter; and

a transmission node coupled to an output of the first transmission gate and an output of the second transmission gate.

2. The data transmission interface according to claim 1, wherein output data is supplied at the transmission node.

3. The data transmission interface according to claim 1, further comprising:

a first inverting logic gate having its input coupled to the transmission node and its output connected to an output node; and

a second inverting logic gate having its output coupled to the transmission node.

4. The data transmission interface according to claim 1, wherein the data transmission interface is configured to transmit data between a source clock domain and a destination clock domain.

5. The data transmission interface according to claim 4, wherein a clock frequency of the source clock domain is slower than a clock frequency of the destination clock domain.

6. The data transmission interface to claim 4, wherein a clock frequency of the source clock domain is faster than a clock frequency of the destination clock domain.

7. The data transmission interface according to claim 4, wherein the source or destination clock domain comprises one or more of the following:

a central processing unit;

a local bus;

a memory cache;

a magnetic storage device;

a random-access memory (RAM);

a communications adapter;

a user interface adapter;

a display adapter; and

a read-only memory (ROM).

8. The data transmission interface according to claim 4, wherein a first latch bank supplies the first transmit data to the master data latch.

9. The data transmission interface according to claim 8, wherein the source clock domain comprises the first latch bank.

10. The data transmission interface of claim 1, further comprising a test input for disabling the third clock signal.

11. The data transmission interface of claim 1, further comprising a test input for disabling the second clock signal.

12. The data transmission interface according to claim 1, further comprising:

a first clock enable signal supplied to the first clock splitter; and

a second clock enable signal supplied to the second clock splitter.

13. The data transmission interface according to claim 1, wherein:

the master data latch is configured according to a level-sensitive scan design (LSSD) master latch implementation; and

the master data latch further receives a scan input.

14. The data transmission interface according to claim 1, wherein the master data latch further receives at least one test input.

15. The data transmission interface according to claim 1, wherein output data is supplied to a downstream logic section.

16. The data transmission interface according to claim 1, wherein:

output data is supplied to a destination latch bank; and

the destination clock domain comprises the destination latch bank.

17. A method of transmitting data between a source clock domain and a destination clock domain, the method comprising:

supplying a first transmit data to a master data latch;

supplying a first clock enable signal to a first clock splitter;

supplying a second clock enable signal to a second clock splitter;

supplying a first clock signal to the master data latch from the first clock splitter;

supplying a second clock signal to a first transmission gate from the first clock splitter;

supplying a third clock signal to a second transmission gate from the second clock splitter; and

supplying a second transmit data to the second transmission gate;

wherein;

the second clock signal and third clock signal are logically mutually exclusive; and

the output of the first transmission gate and the output of a second transmission gate are connected to a transmission node.

18. The method according to claim 17, the method further comprising supplying output data at the transmission node.

19. The method according to claim 17, the method further comprising:

connecting an input of a first inverting logic gate and an output of a second inverting logic gate to the transmission node;

connecting an output of the first inverting logic gate and an input of the second inverting logic gate to an output node; and

supplying output data at the output node.

20. The method according to claim 17, the method further comprising supplying a test signal to the second clock splitter to disable the third clock signal when desired.