Multi-voltage synchronous systems

• US 20090150713A1
• Filed: 01/13/2009
• Published: 06/11/2009
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Mangione-Smith, William Henry
• Granted Patent: US 8,516,300 B2
• Time in Patent Office: Days
• US Class Current: 714/2
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Claims

1. A computing system comprising:

a synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage;

an error detector operable to detect an incidence of a computational error occurring in the first subcircuit; and

a controller operable to change the first power plane voltage based upon the detected incidence of a computational error.

2. The computing system of claim 1, wherein the synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage includes:

a synchronous processor including a first processor core powered by a first power plane having a first power plane voltage and a second processor core powered by a second power plane having a second power plane voltage.

3. The computing system of claim 1, wherein the synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage includes:

a synchronous uniprocessor including a first subsystem powered by a first power plane having a first power plane voltage and a second subsystem powered by a second power plane having a second power plane voltage.

4. The computing system of claim 1, wherein the synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage includes:

a synchronous uniprocessor including a first arithmetic logic unit powered by a first power plane having a first power plane voltage and a second arithmetic logic unit powered by a second power plane having a second power plane voltage.

5. The computing system of claim 1, wherein the synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage includes:

a synchronous uniprocessor including an arithmetic logic unit powered by a first power plane having a first power plane voltage and an on-chip cache powered by a second power plane having a second power plane voltage.

6. The system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

a hardware-implemented error detector operable to detect an incidence of a computational error occurring in the first subcircuit.

7. The system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

one error detector coupled with both the first subcircuit and the second subcircuit, and operable to detect an incidence of a computational error occurring in the first subcircuit.

8. The computing system of claim 7, wherein the one error detector coupled with both the first subcircuit and the second subcircuit, and operable to detect an incidence of a computational error occurring in the first subcircuit includes:

one error detector coupled with both the first subcircuit and the second subcircuit, and operable to detect an incidence of a computational error occurring in the first subcircuit and/or the second subcircuit.

9. The computing system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

a first error detector coupled with the first subcircuit and a second error detector coupled with the second subcircuit, the first error detector and the second error detector respectfully being operable to detect an incidence of a computational error occurring in the first subcircuit and the second subcircuit.

10. The computing system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

an error detector coupled with the controller and operable to detect an incidence of a computational error occurring in the first subcircuit.

12. The computing system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

an error detector operable to detect at least one incidence of a computational error corresponding to a setup/hold violation, a processor clock speed, a processor voltage, a noise spike, a charged particle, a soft error, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, on-chip cache error, an oxide breakdown, an induced error, and/or an electromigration induced error.

13. The computing system of claim 1, wherein the error detector operable to detect an incidence of a computational error occurring in the first subcircuit includes:

an error detector operable to detect at least one of a single incidence, an incidence frequency, an incidence occurrence rate, an incidence tempo, an incidence pattern, and/or an incidence prevalence of a computational error.

14. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller operable to change a first power plane voltage based upon the detected incidence of a computational error without substantially changing the second power plane voltage.

15. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller operable to change a first power plane voltage based upon the detected incidence of a computational error without a logically corresponding change in the second power plane voltage.

16. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller implemented in at least one of hardware, software, firmware, and/or a microengine, and operable to change the first power plane voltage based upon the detected incidence of a computational error.

17. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller implemented in software associated with at least one of an operating system and/or a program executable by the synchronous circuit and operable to change the first power plane voltage based upon the detected incidence of a computational error.

18. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller operable to increase the first power plane voltage based upon the detected incidence of a computational error.

19. The computing system of claim 1, wherein the controller operable to change the first power plane voltage based upon the detected incidence of a computational error includes:

a controller operable to decrease the first power plane voltage based upon the detected incidence of a computational error.

20. The computing system of claim 1, wherein the synchronous circuit, the error detector and the controller are formed on a single chip.

21. The computing system of claim 1, further comprising:

a recovery module operable to cause a correction of the computational error.

22. The computing system of claim 1, further comprising:

a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

23. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller includes:

a power supply operable to provide in response to the controller a selected voltage to the first power plane and another selected voltage to the second power plane.

24. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller includes:

an on-circuit chip power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

25. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller includes:

an off-circuit chip power supply electrically coupled with the circuit and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

26. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller includes:

at least one of a DC/DC regulated, a controllable, and/or programmable power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

27. The computing system of claim 1, further comprising:

a power supply configured to electrically engage a portable power source and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

11. (canceled)

28. A method implemented in a computing system, the method comprising:

detecting a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage; and

increasing the first power plane voltage based upon the detected computational error.

29. The method of claim 28, wherein the detecting a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage further includes:

detecting a computational error occurring in a first processor core of a synchronous processor that includes the first processor core powered by a first power plane at a first power plane voltage and a second processor core powered by a second power plane at a second power plane voltage.

30. The method of claim 28, wherein the detecting a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage further includes:

detecting a computational error occurring in a first subcircuit of a synchronous uniprocessor that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage.

31. The method of claim 28, wherein the increasing the first power plane voltage based upon the detected computational error further includes:

increasing the first power plane voltage based upon the detected computational error while maintaining the second power plane voltage at least substantially constant.

32. The method of claim 28, wherein the increasing the first power plane voltage based upon the detected computational error further includes:

increasing the first power plane voltage based upon the detected computational error without a logically corresponding change in the second power plane voltage.

33. The method of claim 28, further comprising:

operating the first subcircuit at a first power plane voltage.

34. The method of claim 33, wherein the operating the first subcircuit at a first power plane voltage includes:

operating the first subcircuit at an initial first power plane voltage.

35. The method of claim 28, further comprising:

decreasing the first power plane voltage.

36. A computing device comprising:

means for detecting a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage; and

means for increasing the first power plane voltage based upon the detected computational error.

37. The computing device of claim 36, further comprising;

means for operating the first subcircuit at an initial first power plane voltage.

38. The computing device of claim 36, further comprising;

means for decreasing the first power plane voltage.

39. A computing device comprising:

a synchronous circuit including a subcircuit powered by a power plane having a power plane voltage;

an error detector operable to detect an incidence of a computational error attributable to the subcircuit; and

a controller operable to change the power plane voltage of the power plane in response the detected incidence of a computational error.