Nonvolatile memory (NVM) based solid-state disk (SSD) system for scaling and quality of service (QoS) by parallelizing command execution

• US 20090150894A1
• Filed: 12/10/2007
• Published: 06/11/2009
• Est. Priority Date: 12/10/2007
• Status: Abandoned Application

• Current Assignee: Ming Huang, Zhiqing Zhuang
• Original Assignee: Ming Huang, Zhiqing Zhuang
• Inventors: Zhuang, Zhiqing, Huang, Ming
• Application Number:
  US11/953,080
• Publication Number:
  US 20090150894A1
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A method for scaling a SSD system which includes providing at least one storage interface and providing a flexible association between storage commands and a plurality of processing entities via the plurality of nonvolatile memory access channels. Each storage interface associates a plurality of nonvolatile memory access channels.

Claims

1. A method for scaling a SSD system comprising:

providing at least one storage interface, each storage interface associating a plurality of nonvolatile memory access channels, providing a flexible association between storage commands and a plurality of nonvolatile memory modules via the plurality of nonvolatile memory access channels.

2. The method of claim 1 wherein the flexible association is based upon stateful association.

3. The method of claim 1 wherein the flexible association is based upon stateless association.

4. The method of claim 1 wherein the flexible association is based upon storage interface zoning.

5. The method of claim 1 wherein each of the plurality of nonvolatile memory access channels includes a channel context.

6. The method of claim 1 wherein the flexible association is provided via a storage command classification processor and a media processor using both hardware and firmware.

7. The method of claim 1 wherein each of the plurality of nonvolatile memory modules includes a number (Nf) of nonvolatile memory dies or chips.

8. The method of claim 1 wherein the storage interface is one of an ATA/IDE, SATA, SCSI, SAS, Fiber Channel, and iSCSI interface.

9. The channel context of claim 4 comprising:

a channel DMA, a cache, a cache controller, a nonvolatile memory interface controller, and a queue manager.

10. The cache as recited in claim 9, is one of a Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Double Data Rate (DDR) DRAM, and DDR2 DRAM.

11. The cache as recited in claim 9, is of size at least Nf times of 4 KBytes. The cache controller stores write data to the flash module when the collected data size is more than Nf times of 2 KBytes.

12. The method of claim 4 further comprising:

the allocation of resources for system load balancing and for selectively allowing access to data only to certain storage interfaces.

13. The method of claim 6 further comprising:

performing a non-strict classification on a storage command queue;

associating the storage command with one of the plurality of nonvolatile memory access channels based upon the non-strict classification criteria and access address.

14. The method of claim 6 further comprising:

optimistically matching during the non-strict classification to maximize the overall throughput of the access channels.

15. The method of claim 6 wherein:

the non-strict classification includes determining whether to use cache information or nonvolatile memory information during the classification.

16. The command classification processor as recited in claim 6 terminating all the commands other than media read and write commands.

17. The media processor as recited in claim 6 terminating the media read and write commands and arming all the channel DMAs and interface DMAs for media data access.

18. The storage interface as recited in claim 8 having a multi-layer storage protocol processor.

19. The storage protocol processor as recited in claim 18 is one of an ATA/IDE, SATA, SCSI, SAS, Fiber Channel, and iSCSI protocol processor.

20. The storage protocol processor as recited in claim 18 separating the storage commands and data to different FIFO buffers for parallel processing.