System, Structure and Method of Providing Dynamic Optimization of Integrated Circuits Using a Non-Contact Method of Selection, and a Design Structure

• US 20090152543A1
• Filed: 12/17/2007
• Published: 06/18/2009
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Iadanza, Joseph A., Bonaccio, Anthony R.
• Granted Patent: US 7,793,237 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a target performance voltage of the at least one integrated circuit; remotely querying the at least one integrated circuit to obtain the target performance voltage; and providing an operational voltage of a next-level assembly according to the stored target performance voltage.

Claims

1. A method of optimizing an electronic system having at least one integrated circuit, the method comprising:

storing a target performance voltage of the at least one integrated circuit;

remotely querying the at least one integrated circuit to obtain the target performance voltage; and

providing an operational voltage of a next-level assembly according to the stored target performance voltage.

2. The method of claim 1, wherein the target performance voltage is within an optimal supply voltage range for the at least one integrated circuit.

3. The method of claim 1, wherein the at least one integrated circuit is a batch of integrated circuits, various of which are of different technologies, wherein the method further comprises:

testing at least two integrated circuits of the batch of integrated circuits to determine the target performance voltage for each of the at least two integrated circuits;

storing the target performance voltage for each of the at least two integrated circuits on each of the integrated circuits;

querying each of the integrated circuits for the target performance voltage; and

providing the target performance voltage in order to determine that the at least two integrated circuits are compatible for assembly.

4. The method of claim 1, wherein the remotely querying the at least one integrated circuit for the target performance voltage includes querying a radio frequency unit on the at least one integrated circuit by use of RFID technology.

5. The method of claim 1, wherein the storing is provided in a non-volatile memory integrated with the integrated circuit.

6. The method of claim 1, further comprising optimizing an operational voltage or power consumption of the electronic system by using compatible integrated circuits based on compatible operational voltages obtained from the target performance voltage of each of the at least one integrated circuit.

7. The method of claim 1, wherein the storing includes storing a representation of the target performance voltage in a storage unit of the integrated circuit.

8. The method of claim 1, wherein the storing includes programming a non-volatile memory of the at least one integrated circuit with the target performance voltage.

9. The method of claim 1, further comprising testing the at least one integrated circuit until the target performance voltage is achieved.

10. The method of claim 9, wherein the achieving includes incrementing or decrementing a voltage of the at least one integrated circuit to reach the target performance voltage.

11. The method of claim 10, further comprising determining whether the voltage is at a minimum voltage or a maximum voltage, wherein

if the at least one integrated circuit is not at a minimum voltage, decrementing the voltage of the at least one integrated circuit;

and

if the at least one integrated circuit is not at a maximum voltage, incrementing the voltage of the at least one integrated circuit.

12. The method of claim 1, further comprising manufacturing the at least one integrated circuit with a functional unit, a performance monitoring unit, a storage unit and a radio frequency identification unit.

13. A method comprising setting and tracking in a non-contact manner minimum circuit operational voltage of integrated circuits to optimize a voltage/power operating point of an upper level assembly.

14. The method of claim 13, wherein the setting includes storing the operational voltage in a non-volatile memory of the integrated circuits to be assembled in the upper level assembly.

15. The method of claim 13, wherein the tracking include scanning a radio frequency unit of the integrated circuits to be assembled in the upper level assembly.

16. The method of claim 13, further comprising query an RFID tag at card or system level.

17. The method of claim 13, further comprising:

storing the operational voltage of at least one integrated circuit of the integrated circuits in a non-volatile storage unit on the at least one integrate circuit,

remotely querying the at least one integrated circuit to obtain the operational voltage; and

providing the operational voltage of a next-level assembly in response to the remote query in order to determine compatibility between the integrated circuits in a batch.

18. The method of claim 17, further comprising:

testing the at least one integrated circuit until an optimal voltage is achieved, wherein the achieving includes incrementing or decrementing a voltage of the at least one integrated circuit to reach the optimal voltage; and

determining whether the voltage is at a minimum voltage or a maximum voltage, wherein

if the at least one integrated circuit is not at the minimum voltage, decrementing the voltage of the at least one integrated circuit; and

if the at least one integrated circuit is not at the maximum voltage, incrementing the voltage of the at least one integrated circuit.

19. A structure on an integrated circuit comprising:

a non-volatile performance parameter storage unit which is configured to store performance data of the integrated circuit; and

a radio frequency unit configured to provide the performance data stored in the non-volatile performance parameter storage unit upon a non-contact query.

20. The structure of claim 19, further comprising a programming interface, which is configured to interface with the non-volatile performance parameter storage unit and a performance testing unit.

21. The structure of claim 19, further comprising a performance testing unit structured and configured to provide performance data to the non-volatile performance parameter storage unit.

22. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:

a non-volatile performance parameter storage unit which is configured to store performance data of the integrated circuit; and

a radio frequency unit configured to provide the performance date stored in the non-volatile performance parameter storage unit upon a non-contact query.

23. The design structure of claim 22, wherein the design structure comprises a netlist.

24. The design structure of claim 22, wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

25. The design structure of claim 22, wherein the design structure includes at least one item selected from the group consisting of test data files, characterization data, verification data, and design specifications.