ATOMIC LAYER DEPOSITION OF GdScO3 FILMS AS GATE DIELECTRICS

• US 20090152620A1
• Filed: 02/17/2009
• Published: 06/18/2009
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 8,003,985 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: C23C 16/40 Oxides
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/4554 Plasma being used non-continuously in between ALD reactions C23C16/56 takes precedence
• CPC Class Codes: C23C 16/45553 characterized by the use of precursors specially adapted for ALD
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd₂O₃) and scandium oxide (Sc₂O₃) acting as a single dielectric layer with a formula of GdScO₃, and a method of fabricating such a dielectric layer, is described that produces a reliable structure with a high dielectric constant (high k) for use in a variety of electronic devices. The dielectric structure is formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, or as a NROM dielectric, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.

Claims

1. An electronic device comprising:

an amorphous dielectric layer containing an atomic layer deposited dielectric layer of scandium oxide and gadolinium oxide layers in an integrated circuit; and

a conductive layer contacting the dielectric layer.

2. The electronic device of claim 1, wherein the electronic device includes a transistor in the integrated circuit, the transistor having the dielectric layer as a gate insulator and the conductive layer as a gate in the transistor.

3. The electronic device of claim 1, wherein the electronic device includes a CMOS transistor in the integrated circuit, the CMOS transistor having the dielectric layer as a gate insulator and the conductive layer as a gate.

4. The electronic device of claim 3, wherein the electronic device includes a capacitor having the dielectric layer as a dielectric material between two electrodes in the capacitor, and the conductive layer as at least one of the two electrodes.

5. A system comprising:

a controller;

an electronic device coupled to the controller, wherein the electronic device includes;

a dielectric layer comprising an atomic layer deposited dielectric layer of gadolinium oxide and scandium oxide in an integrated circuit; and

a conductive layer contacting the dielectric layer.

6. The system of claim 5, wherein the electronic device includes a memory.

7. A transistor comprising:

a semiconductive substrate having a first type conductivity and first doping level;

at least two regions disposed near a top surface of the semiconductive substrate each having a second type conductivity and a second doping level, the at least two regions separated by a region of the first conductivity type having a first lateral dimension along the top surface of the semiconductive substrate;

a dielectric layer disposed above the top surface of at least a portion of the semiconductive substrate and overlapping at least a portion of each of the at least two regions disposed near a top surface of the semiconductive substrate;

the dielectric layer including at least one scandium oxide layer and at least one gadolinium oxide layer; and

a conductive layer contacting the dielectric layer.

8. The transistor of claim 7, wherein the at least one scandium oxide layer includes an oxide having a formula of Sc₂O₃.

9. The transistor of claim 7, wherein scandium oxide directly contacts the semiconductive substrate.

10. The transistor of claim 7, wherein scandium oxide contacts a diffusion barrier disposed between the scandium oxide and the semiconductive substrate.

11. The transistor of claim 7, wherein the at least one gadolinium oxide includes an oxide having a formula of Gd₂O₃.

12. The transistor of claim 7, wherein gadolinium oxide directly contacts the semiconductive substrate.

13. The transistor of claim 7, wherein gadolinium oxide contacts a diffusion barrier disposed between the scandium oxide and the semiconductive substrate.

14. The transistor of claim 7, wherein the amorphous dielectric layer includes a thickness ratio of Sc₂O₃ to Gd₂O₃ of approximately 1 to 1.

15. The transistor of claim 7, wherein the dielectric layer comprises an amorphous dielectric material.

16. The transistor of claim 15, wherein the substrate is a silicon crystal having a <

100>

crystal orientation at the surface, and the amorphous dielectric layer has an equivalent oxide thickness of 1.0 nm of silicon dioxide.

17. The transistor of claim 7, wherein the dielectric layer comprises a first plurality of scandium oxide layers having a first thickness each interleaved between a second plurality of gadolinium oxide layers having a second thickness.

18. The transistor of claim 7, wherein the conductive layer contacting the dielectric layer is a floating gate disposed below a second dielectric layer and a second conductive layer.

19. The transistor of claim 7, wherein the conductive layer contacting the dielectric layer comprises a refractory material.

20. The transistor of claim 7, wherein the region of the first conductivity type having a first lateral dimension along the top surface of the semiconductive substrate has a first selected doping level at a first end of the lateral dimension and a second selected doping level at a second end of the lateral dimension.

21. A non-volatile transistor comprising:

a semiconductive substrate having a first polarity type conductivity and first doping level;

a first region disposed near a top surface of the semiconductive substrate having a second polarity type conductivity and a second doping level;

a second region disposed near the top surface of the semiconductive substrate having the second polarity type conductivity and having a third doping level;

the second region separated from the first region by a channel region having a selected distance, the channel region having the first conductivity type with a selected fourth doping level adjacent the first region and a selected fifth doping level adjacent the second region;

a first dielectric layer disposed above the top surface of the semiconductive substrate and overlapping at least a portion of the first region and the second region;

a first conductive layer disposed above the first dielectric layer and overlapping at least a portion of the first region and the second region;

a second dielectric layer disposed above the first conductive layer and the first dielectric layer and overlapping at least a portion of the first region and the second region;

a second conductive layer disposed above the second dielectric layer and overlapping at least a portion of the first conductive layer; and

at least one of the first dielectric layer and the second dielectric layer including at least one scandium oxide layer and at least one gadolinium oxide layer.

22. The non-volatile transistor of claim 21, wherein the scandium oxide layer includes an oxide having a formula of Sc₂O₃.

23. The non-volatile transistor of claim 21, wherein the gadolinium oxide includes an oxide having a formula of Gd₂O₃.

24. The non-volatile transistor of claim 21, wherein at least one of the first dielectric layer and the second dielectric layer includes a thickness ratio of Sc₂O₃ to Gd₂O₃ of approximately 1 to 1.

25. The transistor of claim 21, wherein the semiconductive substrate comprises a silicon crystal having a <

100>

crystal orientation at the surface, and the dielectric layer including the Sc₂O₃ to Gd₂O₃ has an equivalent oxide thickness of 1.0 nm of silicon dioxide.

26. The transistor of claim 21, wherein at least one of the first and second dielectric layers comprises an amorphous dielectric material.

27. The transistor of claim 21, wherein the first dielectric layer directly contacts the semiconductive substrate.

28. The transistor of claim 21, wherein the first dielectric layer contacts a diffusion barrier on the semiconductive substrate.

29. The transistor of claim 21, wherein the first dielectric layer is formed of a selected number of layers of scandium oxide and a selected number of layers of gadolinium oxide.

30. The transistor of claim 29, wherein the scandium oxide layers comprise a continuous monolayer.