SEMICONDUCTOR DEVICE

• US 20090152627A1
• Filed: 12/13/2007
• Published: 06/18/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: KIKUCHI, Shuichi, Nakaya, Kiyofumi, Tanaka, Shuji
• Granted Patent: US 7,649,224 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first general conductivity type;

a body layer of a second general conductivity type formed in the semiconductor layer and comprising a channel region;

a source layer formed in the body layer;

a gate electrode disposed on the body layer;

a first well layer of the first general conductivity type formed in the semiconductor layer;

a drain layer of the first general conductivity type formed in the first well layer;

a first withstand voltage boosting layer of the second general conductivity type configured to improve a withstand voltage of the semiconductor device, the first boosting layer being formed in a portion of the semiconductor layer operating as a drift region extending from the drain layer to the body layer;

a second well layer of the first general conductivity type configured to lower an on-resistance and formed in the semiconductor layer under the gate electrode; and

a third well layer of the first general conductivity type configured to lower the on-resistance and formed in the drift region so that the second and third well layers are physically separated from each other.

2. The semiconductor device of claim 1, wherein the third well layer is physically separated from the first well layer.

3. The semiconductor device of claim 1, wherein the first withstand voltage boosting layer is physically in contact with the second well layer.

4. The semiconductor device of claim 1, further comprising a second withstand voltage boosting layer configured to improve the withstand voltage and having an impurity concentration higher than the first boosting layer that is formed in the semiconductor layer between the second well layer and the third well layer.

5. The semiconductor device of claim 1, further comprising a field plate disposed on the first withstand voltage boosting layer, wherein an edge of the field plate extends beyond an edge of the third well layer toward the drain layer.

6. The semiconductor device of claim 1, wherein the third well layer and the first withstand voltage boosting layer are superimposed.

7. The semiconductor device of claim 1, further comprising a field insulation film formed in the semiconductor layer between the drain layer and the third well layer, wherein the first withstand voltage boosting layer and the third well layer are physically separated from the field insulation film.

8. The semiconductor device of claim 7, further comprising a field plate disposed on the first withstand voltage boosting layer and extending toward the drain layer so as to cover at least part of the field insulation film.