SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

• US 20090152631A1
• Filed: 02/11/2009
• Published: 06/18/2009
• Est. Priority Date: 10/09/1992
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEMURA, Yasuhiko, ZHANG, Hongyong, TERAMOTO, Satoshi
• Granted Patent: US 7,723,788 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 μm or less in width, and allowing the metal to react with silicon.

Claims

1. A semiconductor device comprising:

a thin film transistor comprising;

a semiconductor layer formed on an insulating surface;

a pair of first impurity regions formed in the semiconductor layer;

a pair of second impurity regions formed between the pair of first impurity regions;

a channel region formed between the pair of second impurity regions;

a pair of metal silicide regions formed on the pair of first impurity regions;

a gate insulating film formed over the semiconductor layer;

a gate electrode formed over the gate insulating film;

a pair of side walls adjacent to the gate electrode;

a first insulating film provided between the gate electrode and the pair of side walls;

a second insulating film formed over the gate electrode the first insulating film and the pair of side walls; and

an electrode formed over the second insulating film and electrically connected to one of the pair of metal silicide regions,

wherein the pair of side walls is contact with end portions of the gate insulating film, and

wherein a maximum width of each of the pair of side walls is larger than a width of the first insulating film between the gate electrode and each of the pair of side walls in a channel direction.

2. A semiconductor device according to claim 1, wherein the first insulating film comprises an oxide of the gate electrode.

3. A semiconductor device according to claim 1, wherein the first insulating film comprises an anodic oxide of the gate electrode.

4. A semiconductor device according to claim 1, wherein the semiconductor layer has a thickness of 50 nm or less.

5. A semiconductor device according to claim 1, wherein the pair of metal silicide regions is in contact with the pair of first impurity regions and the pair of second impurity regions.

13. A semiconductor device according to claim 1, wherein the pair of metal silicide regions includes at least any one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

6. A semiconductor device comprising:

a n-type thin film transistor comprising;

a first semiconductor layer formed on an insulating surface;

a pair of first impurity regions formed in the first semiconductor layer;

a pair of second impurity regions formed between the pair of first impurity regions;

a first channel region formed between the pair of second impurity regions;

a pair of metal silicide regions formed on the pair of first impurity regions;

a first gate insulating film formed over the first semiconductor layer;

a first gate electrode formed over the first gate insulating film;

a pair of first side walls adjacent to the first gate electrode;

a first insulating film provided between the first gate electrode and the pair of first side walls;

a second insulating film formed over the first gate electrode, the first insulating film and the pair of first side walls; and

a first electrode formed over the second insulating film and electrically connected to one of the pair of first metal silicide regions,

a p-type thin film transistor comprising;

a second semiconductor layer formed on the insulating surface;

a pair of third impurity regions formed in the second semiconductor layer;

a pair of fourth impurity regions formed between the pair of third impurity regions;

a second channel region formed between the pair of fourth impurity regions;

a pair of second metal silicide regions formed on the pair of third impurity regions;

a second gate insulating film formed over the second semiconductor layer;

a second gate electrode formed over the second gate insulating film;

a pair of second side walls adjacent to the second gate electrode;

a third insulating film provided between the second gate electrode and the pair of second side walls;

a fourth insulating film formed over the second gate electrode, the third insulating film and the pair of second side walls; and

an second electrode formed over the fourth insulating film and electrically connected to one of the pair of second metal silicide regions,

wherein the first gate insulating film and the second gate insulating film are identical,

wherein the first gate electrode and the second gate electrode are identical,

wherein the second insulating film and the fourth insulating film are identical,

wherein the pair of first side walls is contact with end portions of the first gate insulating film, and

wherein a maximum width of each of the pair of second side walls is larger than a width of the third insulating film between the second gate electrode and each of the pair of second side walls in a second channel direction.

7. A semiconductor device according to claim 6, wherein the first insulating film and the third insulating film comprise an oxide of the first gate electrode.

8. A semiconductor device according to claim 6, wherein the first insulating film comprises an anodic oxide of the gate electrode.

9. A semiconductor device according to claim 6, wherein the third insulating film comprises an anodic oxide of the second gate electrode.

10. A semiconductor device according to claim 6, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of 50 nm or less.

11. A semiconductor device according to claim 6, wherein the pair of first metal silicide regions is in contact with the pair of first impurity regions and the pair of second impurity regions.

12. A semiconductor device according to claim 6, wherein the pair of second metal silicide regions is in contact with the pair of third impurity regions and the pair of fourth impurity regions.

14. A semiconductor device according to claim 6, wherein the pair of first metal silicide regions and the pair of the second metal silicide regions include at least any one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.