Semiconductor device

• US 20090152674A1
• Filed: 11/24/2008
• Published: 06/18/2009
• Est. Priority Date: 12/14/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Uchida, Shinichi, Nakashiba, Yasutaka
• Granted Patent: US 7,999,386 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19015 including thin film passive components

Abstract

A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the inductor in a plan view, and isolating the inductor from other regions, wherein the guard ring contains an annular impurity diffused layer provided in the surficial portion of the semiconductor substrate, and an annular electro-conductor connected to the impurity diffused layer, and extended across a plurality of interconnect layers, up to a layer having a level of height not lower than the layer having the inductor provided therein.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of insulating interlayers formed over said semiconductor substrate, and containing a plurality of interconnect layers;

an inductor formed over said semiconductor substrate while placing at least one of said insulating interlayers in between; and

a guard ring surrounding said inductor in a plan view, so as to isolate said inductor from other regions,

wherein said guard ring comprises;

an annular impurity diffused layer provided in the surficial portion of said semiconductor substrate; and

an annular electro-conductor connected to said impurity diffused layer, and extended across said plurality of interconnect layers in said plurality of insulating interlayers, up to a layer having a level of height not lower than the layer having said inductor provided therein.

2. The semiconductor device as claimed in claim 1,

wherein said electro-conductor of said guard ring is extended up to a layer having a level of height higher than the layer having said inductor provided therein.

3. The semiconductor device as claimed in claim 1,

wherein said guard ring is formed over said semiconductor substrate while placing a plurality of said insulating interlayers in between.

4. The semiconductor device as claimed in claim 1,

wherein said guard ring is applied with a reference potential.

5. The semiconductor device as claimed in claim 4,

wherein said semiconductor substrate has a plurality of transistors formed thereon, also said transistors being applied with the reference potential respectively, and

over said semiconductor substrate, said guard ring is applied with the reference potential through a route different from a route through which said plurality of transistors are applied with said reference potential.

6. The semiconductor device as claimed in claim 1,

further comprising a buried insulating film provided in the surficial portion of said semiconductor substrate, in a region overlapping said inductor in a plan view.

7. The semiconductor device as claimed in claim 6,

wherein said buried insulating film is provided over the entire portion of the region overlapping said inductor in a plan view.

8. The semiconductor device as claimed in claim 6,

wherein said buried insulating film is provided in the region overlapping said inductor in a plan view, so as to allow the surface of said semiconductor substrate to expose like islands.

9. The semiconductor device as claimed in claim 1,

further comprising a plurality of dummy metals dispersively arranged in said insulating interlayers in a plan view,

wherein, in a plan view, mean distance of every adjacent dummy metals is larger in the internal area of said guard ring than in the external area of said guard ring.