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SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP

  • US 20090153253A1
  • Filed: 12/17/2007
  • Published: 06/18/2009
  • Est. Priority Date: 12/17/2007
  • Status: Active Grant
First Claim
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1. A phase locked loop comprising a delay circuit coupled along a feedback path of the phase locked loop, the delay circuit operable to delay a feedback clock signal between about 20% and about 70% of a period of a reference signal that is applied to the phase locked-loop.

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