SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP

• US 20090153253A1
• Filed: 12/17/2007
• Published: 06/18/2009
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mei, Shizhong
• Granted Patent: US 7,969,252 B2
• Time in Patent Office: Days
• US Class Current: 331/10
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.

Claims

1. A phase locked loop comprising a delay circuit coupled along a feedback path of the phase locked loop, the delay circuit operable to delay a feedback clock signal between about 20% and about 70% of a period of a reference signal that is applied to the phase locked-loop.

2. The phase locked loop of claim 1 wherein the delay is adjustable.

3. The phase locked loop of claim 1 wherein the delay circuit comprises a switch operable to disable and enable the delay.

4. The phase locked loop of claim 3 wherein the delay is disabled after the phase locked loop has locked.

5. A phase locked loop, comprising:

a phase detector having a first input terminal operable to receive an external clock signal, and a second input terminal, the phase detector further operable to generate a phase error signal;

a voltage controlled oscillator coupled to receive the phase error signal from the phase comparison circuit, the voltage controlled oscillator operable to generate an output clock signal, the output clock signal having a frequency corresponding to the phase error signal;

a feedback path coupling a clock feedback signal to the second input terminal of the phase comparison circuit, the clock feedback signal having a phase and a frequency that are determined by the phase and the frequency of the output clock signal; and

a delay circuit in the feedback path between the voltage controlled oscillator and the phase comparison circuit.

6. The phase locked loop of claim 5 wherein the delay circuit is adjustable.

7. The phase locked loop of claim 6 wherein the delay circuit is adjustable as a function of a loop gain of the phase locked loop system.

8. The phase locked loop of claim 5 wherein the delay circuit delays the clock feedback signal between about 20% and about 70% of the external clock signal.

9. The phase locked loop of claim 8 wherein the delay circuit delays the clock feedback signal between about 30% and about 60% of the external clock signal.

10. The phase locked loop of claim 5 wherein the delay circuit comprises a bypass path operable to disable the delay when the bypass path is enabled.

11. The phase locked loop of claim 10 wherein the bypass path is enabled after the phase lock loop is locked.

16. The phase locked loop of claim 10 wherein the bypass path is enabled after the phase lock loop is locked.

12. A memory device, comprising:

an array of memory cells; and

a phase locked loop, comprising;

a phase detector having a first input terminal operable to receive an external clock signal, and a second input terminal, the phase detector further operable to generate a phase error signal;

a voltage controlled oscillator coupled to receive the phase error signal from the phase comparison circuit, the voltage controlled oscillator operable to generate an output clock signal, the output clock signal having a frequency corresponding to the phase error signal;

a feedback path coupling a clock feedback signal to the second input terminal of the phase comparison circuit, the clock feedback signal having a phase and a frequency that are determined by the phase and the frequency of the output clock signal; and

a delay circuit in the feedback path between the voltage controlled oscillator and the phase comparison circuit.

13. The memory device of claim 12 wherein the delay circuit is adjustable as a function of the loop gain of the phase locked loop system.

14. The memory device of claim 12 wherein the delay circuit is operable to delay the feedback clock signal between 20% and 70% of the external clock signal.

15. The memory device of claim 12 wherein the delay circuit comprises a bypass path operable to selectively disable the delay.

17. A method of reducing lock time in a phase locked loop, comprising:

generating a feedback clock signal;

delaying the feedback clock signal between about 20% and about 70% of a period of an external clock signal to provide a delayed clock signal;

generating a phase error signal by comparing a phase of the delayed clock signal to a phase of the external clock signal; and

increasing a loop gain based on the phase error signal.

18. The method of claim 17 wherein the act of delaying the feedback clock signal between about 20% and about 70% of the period of the external clock signal comprises delaying the feedback clock signal between about 30% and about 60% of the period of the external clock signal.

19. The method of claim 17 wherein the act of delaying the feedback clock signal between about 20% and about 70% of the period of the external clock comprises adjusting the delay of the feedback clock signal as a function of whether or not the phase locked loop is locked.

20. The method of claim 19 wherein the act of adjusting the feedback clock signal comprises adjusting the delay of the feedback clock signal as a function of whether or not the phase locked loop is locked.

21. The method of claim 19 wherein the act of adjusting the delay of the feedback clock signal comprises adjusting the delay of the feedback clock signal as a function of a magnitude of a loop gain of the phase locked loop.

22. The method of claim 17 further comprising reducing or removing the delay by reducing the charge pump current.

23. A method of decreasing lock time of a phase locked loop, comprising:

increasing a loop gain; and

adding a delay to a feedback clock signal along a feedback path of the phase locked loop, the delay being between about 20% and about 70% of a period of a reference clock signal.

24. The method of claim 23 wherein the delay is between about 30% and about 60% of the period of the reference clock signal.

25. The method of claim 23 further comprising removing the delay once the phase locked loop locks.