METHOD AND SYSTEM FOR MATCHING NETWORKS EMBEDDED IN AN INTEGRATED CIRCUIT PACKAGE

• US 20090153261A1
• Filed: 12/13/2007
• Published: 06/18/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Rofougaran, Ahmadreza
• Granted Patent: US 8,115,567 B2
• Time in Patent Office: Days
• US Class Current: 333/33
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H03H 7/38 : Impedance-matching networks

Abstract

Methods and systems for matching networks embedded in an integrated circuit package are disclosed and may include controlling impedance within an integrated circuit via one or more impedance matching networks. The impedance matching networks may be embedded within a multi-layer package bonded to the integrated circuit. The impedance of one or more devices within the integrated circuit may be configured utilizing the impedance matching networks. The multi-layer package may include one or more impedance matching networks. The impedance matching networks may provide impedance matching between devices internal to the integrated circuit and external devices. The impedance matching networks may be embedded within the multi-layer package, and may include transmission lines, inductors, capacitors, transformers and/or surface mount devices. The impedance matching networks may be deposited on top of and/or on bottom of the multi-layer package. The integrated circuit may be flip-chip bonded to the multi-layer package.

Claims

1. A method for enabling communication, the method comprising:

controlling impedance within an integrated circuit via one or more impedance matching networks, wherein said one or more impedance matching networks are embedded within a multi-layer package bonded to said integrated circuit.

2. The method according to claim 1, comprising configuring the impedance of one or more devices within said integrated circuit utilizing said impedance matching networks.

3. The method according to claim 1, wherein said impedance matching networks are embedded within said multi-layer package.

4. The method according to claim 1, wherein said impedance matching networks comprise transmission lines.

5. The method according to claim 1, wherein said impedance matching networks comprise inductors.

6. The method according to claim 1, wherein said impedance matching networks comprise capacitors.

7. The method according to claim 1, wherein said impedance matching networks comprise transformers.

8. The method according to claim 1, wherein said impedance matching networks comprise surface mount devices.

9. The method according to claim 1, wherein said impedance matching networks are fabricated on top of and/or on bottom of said multi-layer package.

10. The method according to claim 1, wherein said integrated circuit is flip-chip bonded to said multi-layer package.

11. A system for enabling communication, the system comprising:

a multi-layer package that is bonded to an integrated circuit, wherein said multi-layer package comprises one or more impedance matching networks.

12. The system according to claim 11, wherein devices internal to said integrated circuit are impedance matched to external devices utilizing said impedance matching networks.

13. The system according to claim 11, wherein said impedance matching networks are embedded within said multi-layer package.

14. The system according to claim 11, wherein said impedance matching networks comprise transmission lines.

15. The system according to claim 11, wherein said impedance matching networks comprise inductors.

16. The system according to claim 11, wherein said impedance matching networks comprise capacitors.

17. The system according to claim 11, wherein said impedance matching networks comprise transformers.

18. The system according to claim 11, wherein said impedance matching networks comprise surface mount devices.

19. The system according to claim 11, wherein said impedance matching networks are fabricated on top of and/or on bottom of said multi-layer package.

20. The system according to claim 11, wherein said integrated circuit is flip-chip bonded to said multi-layer package.