MEMORY ARRAYS USING NANOTUBE ARTICLES WITH REPROGRAMMABLE RESISTANCE

• US 20090154218A1
• Filed: 01/15/2009
• Published: 06/18/2009
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: HUANG, X. M. Henry, SIVARAJAN, Ramesh, RUECKES, Thomas, BERTIN, Claude L., STRASBURG, Max, KONSEK, Steven L., MEINHOLD, Mitchell, GUO, Frank
• Granted Patent: US 8,580,586 B2
• Time in Patent Office: Days
• US Class Current: 365/129
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Claims

1. A method of operating a two terminal nanotube memory cell comprising:

applying a first electrical stimulus to change the resistance of a nanotube article between a first terminal and a second terminal to a relatively high resistance; and

applying a second electrical stimulus to change the resistance of the nanotube article between the first and second terminals to a relatively low resistance,

wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.

2. The method of claim 1, wherein the first and second informational states are nonvolatile.

3. The method of claim 1, wherein the resistance of the first state is at least about ten times larger than the resistance of the second state.

4. The method of claim 1, wherein the nanotube article comprises a region of nanotube fabric of defined orientation.

5. The method of claim 1, wherein the first and second terminals are metal.

6. The method of claim 1, wherein the metal comprises at least one Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, and TiW.

7. The method of claim 1, wherein the two terminal memory cell receives a bit line, a first word line, and a second word line.

8. The method of claim 7 comprising:

applying a select voltage to the first word line to select the cell and program voltage to the bit line to change the resistance of the nanotube article to a relatively low resistance.

9. The method of claim 7 comprising:

applying a select voltage to the first word line to select the cell; and

applying an erase voltage to the bit line to change the resistance of the nanotube article to a relatively high resistance value.

10. The method of claim 7 comprising:

reading an informational state of the memory cell.

11. The method of claim 10 wherein reading the informational state of the memory cell comprises:

selecting the cell by activating one of the bit line and the first word line; and

applying a read stimulus to the bit line.

12. The method of claim 11 wherein applying a read stimulus to the bit line comprises:

applying a floating voltage; and

determining whether the voltage on the bit line decays below a threshold value.

13. The array of claim 1, comprising producing an erase operation for the first electrical stimulus.

14. The array of claim 13, wherein producing an erase operation comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the memory cell to the first informational state.

15. The array of claim 1, producing a program operation for the second electrical stimulus.

16. The array of claim 15, wherein producing the program operation comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the device to the second informational state.

17. The array of claim 7, comprising:

applying a select voltage to the first word line to select the cell; and

applying an erase voltage to the second word line to change the resistance of the nanotube article to a relatively high resistance.

18. The array of claim 7 comprising:

applying a select voltage to the first word line to select the cell; and

applying a program voltage to the second word line to change the resistance of the nanotube article to a relatively low resistance.