NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20090154237A1
• Filed: 11/25/2008
• Published: 06/18/2009
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TOKIWA, Naoya
• Granted Patent: US 7,864,586 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;

a first register group configured to store control data used for controlling memory operations;

an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and

a second register group configured to store the adjusting data read from the adjusting data storage area.

2. The non-volatile semiconductor memory device according to claim 1, further comprising:

a voltage generating circuit configured to generate multiple voltages required correspondingly to the memory operations, wherein

the control data are voltage trimming data to be supplied to the voltage generating circuit, the voltage trimming data being preliminarily written in the memory cell array and read out to be held in the first register group at a power-on reset time.

3. The non-volatile semiconductor memory device according to claim 2, wherein

the adjusting data storage area is set in a user-accessible area in the memory cell array, and the adjusting data contain voltage adjusting data used for adjusting the voltage trimming data, the voltage adjusting data being read out prior to a normal data read, write or erase operation and held in the second register group.

4. The non-volatile semiconductor memory device according to claim 3, wherein

the voltage trimming data held in the first register group are adjusted by the corresponding voltage adjusting data held in the second register group and applied to the voltage generating circuit.

5. The non-volatile semiconductor memory device according to claim 1, further comprising:

a first address register part configured to store first address data input for normally data-reading, data-writing or data-erasing; and

a second address register part configured to store second address data input for accessing the adjusting data storage area.

6. The non-volatile semiconductor memory device according to claim 5, wherein

the second address data is input for reading the adjusting data previously to the first address data in a normal data read, write or erase operation.

7. The non-volatile semiconductor memory device according to claim 3, wherein

the user-accessible area comprises a plurality of block groups, each of which includes multiple blocks, specified blocks, to which specified addresses are assigned in the respective block groups, constituting the adjusting data storage area.

8. The non-volatile semiconductor memory device according to claim 5, wherein

the second address register part is an address output circuit configured to output the second address data, which are fixedly set.

9. The non-volatile semiconductor memory device according to claim 1, wherein

the memory cell array comprises NAND cell units arranged therein, the NAND cell unit having a plurality of the memory cells connected in series.

10. The non-volatile semiconductor memory device according to claim 9, wherein

the memory cell stores multiple bits.

11. A non-volatile semiconductor memory device comprising:

a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;

a voltage generating circuit configured to generate multiple voltages required correspondingly to the memory operations;

a first register group configured to store voltage trimming values supplied to the voltage generating circuit; and

a second register group configured to store voltage adjusting values used for adjusting the voltage trimming values.

12. The non-volatile semiconductor memory device according to claim 11, wherein

the voltage trimming values are preliminarily written in a ROM fuse area disposed in the memory device and read out to be held in the first register group at a power-on reset time.

13. The non-volatile semiconductor memory device according to claim 11, wherein

the voltage adjusting values are preliminarily stored in a specified user-accessible area defined in the memory cell array, and read out in accordance with a specified access cycle to be held in the second register group.

14. The non-volatile semiconductor memory device according to claim 13, further comprising:

a first address register part configured to store first address data input for normally data-reading, data-writing or data-erasing; and

a second address register part configured to store second address data input for reading the voltage adjusting values in the specified user-accessible area.

15. The non-volatile semiconductor memory device according to claim 14, wherein

the specified access cycle is performed previously to the first address data input.

16. The non-volatile semiconductor memory device according to claim 13, wherein

the specified user-accessible area is formed of specified blocks with specified addresses assigned in a plurality of block groups, each of which includes multiple blocks.

17. The non-volatile semiconductor memory device according to claim 14, wherein

the second address register part is an address output circuit configured to output the second address data, which are fixedly set.

18. The non-volatile semiconductor memory device according to claim 11, wherein

the memory cell array comprises NAND cell units arranged therein, the NAND cell unit having a plurality of the memory cells connected in series.

19. The non-volatile semiconductor memory device according to claim 18, wherein

the memory cell stores multiple bits.