PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS

• US 20090154238A1
• Filed: 02/10/2009
• Published: 06/18/2009
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, June
• Granted Patent: US 7,738,294 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution.

Claims

1. A method of programming a memory device having an array of one or more multilevel memory cells each configured to store 2^N data states each corresponding to a pattern of N bits, each data state assigned a non-overlapping threshold voltage range, where N is an integer value equal to or greater than 2, the method comprising:

shifting the threshold voltages of the one or more multilevel memory cells to an initial threshold voltage range;

if N is greater than 2, for i=1 to N−

2, shifting a memory cell'"'"'s threshold voltage (Vt) by 2<sup>N−

i</sup> threshold voltage ranges if it is desired to change the i^th bit of the pattern of N bits, wherein i is an integer value;

subsequently shifting the memory cell'"'"'s Vt by one threshold voltage range if it is desired to change a next to last bit of the pattern of N bits; and

subsequently shifting the memory cell'"'"'s Vt by two threshold voltage ranges if it is desired to change a last bit of the pattern of N bits.

2. The method of claim 1, wherein shifting the memory cell'"'"'s Vt further comprises shifting the memory cell'"'"'s Vt by performing a programming operation on the memory cell.

3. The method of claim 2, further comprising biasing a bit line coupled to the memory cell to alter a rate of change of the memory cell'"'"'s threshold voltage.

4. The method of claim 3, further comprising applying one or more programming pulses to the memory cell to shift the threshold voltage of the memory cell.

5. The method of claim 4, further comprising, performing a first verify operation following each applied programming pulse to determine if the memory cell threshold voltage exceeds a first verify voltage.

6. The method of claim 5, further comprising biasing the bit line coupled to the memory cell to alter the rate of change of the threshold voltage of the memory cell if the first verify operation determines that the memory cell threshold voltage exceeds the first verify voltage.

7. The method of claim 6, further comprising performing a second verify operation following each applied programming pulse to determine if the memory cell threshold voltage has achieved a threshold voltage level of the memory cell'"'"'s intended threshold voltage range.

8. The method of claim 7, further comprising biasing the bit line coupled to the memory cell to inhibit a change of the threshold voltage of the memory cell coupled to the bit line if the memory cell has achieved a threshold voltage of the memory cell'"'"'s intended threshold voltage range.

9. The method of claim 1, wherein shifting the threshold voltages of the one or more multilevel memory cells to the initial threshold voltage range further comprises shifting the threshold voltages to a threshold voltage range corresponding to an erased data state.

10. A method for programming a memory cell, comprising:

if it is desired to alter a first page of a data value of the memory cell, shifting the memory cell from a first data state to a second data state; and

if it is desired to alter a second page of the data value of the memory cell, shifting the memory cell to a third data state if the memory cell is in the first data state and shifting the memory cell to a fourth data state if the memory cell is in the second data state;

wherein the first, second, third and fourth data states correspond to increasing and non-overlapping ranges of threshold voltages for the memory cell.

11. The method of claim 10, wherein the first page of the data value comprises a least significant page of the data value and the second page of the data value comprises a most significant page of the data value.

12. The method of claim 10, wherein shifting the memory cell to a third data state if the memory cell is in the first data state and shifting the memory cell to a fourth data state if the memory cell is in the second data state comprises controlling the shifting of memory cells from the first data state to the third data state and controlling the shifting of memory cells to the fourth data state from the second data state such that memory cells shifting to the third data state reach the third data state at approximately the same time as memory cells shifting to the fourth data state reach the fourth data state.

13. A memory device, comprising:

an array of one or more multilevel memory cells each configured to store 2^N data states, each data state assigned a non-overlapping threshold voltage range, where N is an integer value equal to or greater than 2; and

control circuitry, wherein the control circuitry, during programming of a memory cell, is configured to;

shift the threshold voltages of the one or more multilevel memory cells to an initial threshold voltage range;

if N is greater than 2, for i=1 to N−

2, shift a memory cell'"'"'s threshold voltage (Vt) by 2<sup>N−

i</sup> threshold voltage ranges if it is desired to change the i^th bit of the pattern of N bits, wherein i is an integer value;

subsequently shift the memory cell'"'"'s Vt by one threshold voltage range if it is desired to change a next to last bit of the pattern of N bits; and

subsequently shift the memory cell'"'"'s Vt by two threshold voltage ranges if it is desired to change a last bit of the pattern of N bits.

14. The memory device of claim 13, wherein the control circuitry is further configured to shift the memory cell'"'"'s Vt to a higher threshold voltage when shifting the memory cell'"'"'s Vt by one or more threshold voltage ranges during programming of the memory cell.

15. The memory device of claim 13, wherein the control circuitry is further configured to alter a rate of change of the memory cell'"'"'s Vt during different portions of the programming of the memory cell.

16. A memory device, comprising:

an array of memory cells logically arranged in rows and in columns; and

control circuitry, wherein the control circuitry is configured to;

shift a memory cell from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell; and

shift the memory cell to a third data state if the memory cell is in the first data state and shift the memory cell to a fourth data state if the memory cell is in the second data state, if it is desired to alter a second digit of the data value of the memory cell;

wherein each data state is represented by a range of threshold voltages for each memory cell of the array of the memory cells; and

wherein the first, second, third and fourth data states correspond to increasing and non-overlapping ranges of threshold voltages for each memory cell.

17. The memory device of claim 16, further comprising a bit line coupled to each column of memory cells, wherein the control circuitry is further configured to shift the threshold voltages of one or more memory cells of a row of memory cells by performing a programming operation on the row of memory cells.

18. The memory device of claim 17, wherein the control circuitry is further configured to bias one or more of the bit lines coupled to columns of memory cells containing the row of memory cells to inhibit programming of any memory cell of the row of memory cells where programming is not desired during a programming operation performed on the row of memory cells.

19. The memory device of claim 17, wherein the control circuitry is further configured to bias one or more of the bit lines to alter a rate of change of the threshold voltage of a memory cell of the row of memory cells coupled to those bit lines during a programming operation performed on the row of memory cells.

20. The memory device of claim 19, wherein the control circuitry is further configured to alter the rate of change of the threshold voltage of each memory cell to be programmed to the third data state or to the fourth data state such that the memory cells to be programmed to the third data state or the fourth data state achieve their respective desired threshold voltage levels at approximately the same time.

21. The memory device of claim 17, wherein the control circuitry is further configured to perform a first verify operation to determine if a memory cell threshold voltage has exceeded a particular threshold voltage where the particular threshold voltage is less than any threshold voltage of the memory cell'"'"'s intended threshold voltage range.

22. The memory device of claim 21, wherein the control circuitry is further configured to perform a second verify operation to determine if a memory cell threshold voltage has achieved a threshold voltage level of the memory cell'"'"'s intended threshold voltage range after achieving the particular threshold voltage.

23. The memory device of claim 22, wherein the control circuitry is further configured to alter a rate of change of a memory cell threshold voltage if the memory cell threshold voltage exceeds the particular threshold voltage level corresponding to the first verify operation.

24. The memory device of claim 23, wherein the control circuitry is further configured to inhibit further programming of a memory cell which passes the second verify operation for a remainder of the programming operation.

25. The memory device of claim 17, wherein the control circuitry is further configured to selectively bias each bitline at one of a ground potential, a bias level which alters a rate of change of a memory cell coupled to the bit line during a programming operation performed on the memory cell and a bias level which inhibits programming of a memory cell coupled to the bit line.