SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME

• US 20090154252A1
• Filed: 12/11/2008
• Published: 06/18/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIBATA, Noboru
• Granted Patent: US 7,995,392 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Claims

1. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and

a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in a first erase operation, erases an n number of memory cells (n is a natural number equal to or larger than

     2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation at a first verify level, finds the number of cells k (k≦

n) (k is a natural number equal to or larger than

     1) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out a second erase operation using the second erase voltage.

2. The semiconductor memory device according to claim 1, wherein the control circuit sets the second erase voltage high when the number of cells k is equal to or larger than a specified value.

3. The semiconductor memory device according to claim 1, wherein the control circuit, after the second erase operation, carries out a verify operation at a second verify level.

4. The semiconductor memory device according to claim 1, wherein the n number of memory cells are composed of an m number of segments each having n/m (m<

n) cells and, in the segments each including a k number of cells exceeding the first verify level, a segment where the number of cells exceeding the first verify level is equal to or larger than a specified value (the specified value is equal to or more than

     1) is erased in an erase operation using the second erase voltage and the other segments are unerased.

5. The semiconductor memory device according to claim 1, wherein the first erase voltage is lower than the second erase voltage.

6. The semiconductor memory device according to claim 1, further comprising carries out a second verify operation after the second erase operation, and carries out an erase operation when a result of the second erase operation does not satisfy a condition.

7. The semiconductor memory device according to claim 6, wherein the first verify level is higher than the second verify level.

8. The semiconductor memory device according to claim 1, wherein the verify operation is performed simultaneously on a plurality of memory cells connected to a plurality of bit lines.

9. The semiconductor memory device according to claim 1, wherein the verify operation is performed on cells connected to one of 2 bit lines adjacent to each other and, is performed on cells connected to another one of 2 bit lines.

10. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and

a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in an erase operation, erases said plurality of memory cells simultaneously, and verifies the threshold voltage of a memory cell selected by a specific one of the word lines using a first verify level, the first verify level being shifted by a second verify level in verifying all the word line simultaneously.

11. The semiconductor memory device according to claim 10, wherein the first erase voltage is lower than the second erase voltage.

12. The semiconductor memory device according to claim 10, wherein the first erase verify level is higher than the second verify level.

13. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and

a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines,

wherein, in an erase operation, the control circuit erases said plurality of memory cells connected to n word lines of the plurality of word lines simultaneously, and carries out a verify operation to determine whether the threshold voltage of a memory cell selected by a specific word line of the n word lines has reached a threshold level in the erase operation using a first verify level.

14. The semiconductor memory device according to claim 13, wherein a voltage lower than an applied voltage is applied to a memory cell adjacent to the memory cell selected by the specific word line in a read operation.

15. The semiconductor memory device according to claim 13, wherein the specific word line is one or a plurality of word lines.

16. The semiconductor memory device according to claim 13, wherein the specific word line is at least three word lines adjacent to one another.

17. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and

a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines,

wherein, in an erase operation, the control circuit erases said plurality of memory cells connected to n word lines of the plurality of word lines simultaneously and then performs a write operation on said plurality of memory cells connected to the n word lines simultaneously, and carries out a verify operation to determine whether the threshold voltage of a memory cell selected by a specific word line of the n word lines has reached a threshold level using a first verify level.

18. The semiconductor memory device according to claim 17, a voltage lower than an applied voltage being applied to a memory cell adjacent to the memory cell selected by the specific word line in a read operation.

19. The semiconductor memory device according to claim 17, wherein the specific word line is one or a plurality of word lines.

20. The semiconductor memory device according to claim 17, wherein the specific word line is at least three word lines adjacent to one another.