MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT
First Claim
1. A memory comprising:
- a plurality of memory cells each comprising a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail to the true data input and to the complementary data input;
a test circuit comprising a plurality of test cells, each test cell comprising a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell to form a looped chain, each test cell comprising a first inverter connected between the true data input and the complementary data input.
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Abstract
A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.
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Citations
20 Claims
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1. A memory comprising:
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a plurality of memory cells each comprising a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail to the true data input and to the complementary data input; a test circuit comprising a plurality of test cells, each test cell comprising a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell to form a looped chain, each test cell comprising a first inverter connected between the true data input and the complementary data input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification