Method for fabricating pitch-doubling pillar structures

• US 20090155962A1
• Filed: 12/17/2007
• Published: 06/18/2009
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Radigan, Steven J., Petti, Christopher J.
• Granted Patent: US 7,759,201 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

Claims

1. A method of making a semiconductor device, comprising:

forming at least one device layer over a substrate;

forming at least two spaced apart features over the at least one device layer;

forming sidewall spacers on the at least two features;

filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature;

selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other; and

etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

2. The method of claim 1, wherein the at least two spaced apart features comprise a plurality of features.

3. The method of claim 2, further comprising:

filling each space between each two adjacent features of the plurality of features with one of a plurality of filler features; and

etching the at least one device layer using the plurality of features and the plurality of filler features as a mask.

4. The method of claim 2, wherein the step of forming sidewall spacers comprises forming the sidewall spacers on the plurality of features, such that the sidewalls spacers on adjacent features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers.

5. The method of claim 1, wherein:

the at least two features and the filler feature comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing comprises selectively etching the second material of the sidewall spacers without substantially removing the first material.

6. The method of claim 1, wherein:

the at least two features comprise a first material, the filler feature comprises a second material and the sidewall spacers comprise a third material different from the first and the second material; and

the step of selectively removing comprises selectively etching the third material of the sidewall spacers without substantially removing the first or the second material.

7. The method of claim 1, wherein the step of filling the space between the first sidewall spacer on the first feature and the second sidewall spacer on the second feature with the filler feature comprises forming a filler film over the first and the second features and planarizing the filler film to expose upper portions of the first and the second features and upper portions of the sidewall spacers.

8. The method of claim 1, wherein:

the at least two features comprise an electrically conductive material covered by a hard mask material;

the filler feature comprises the electrically conductive material; and

the sidewall spacers comprise an electrically insulating material.

9. The method of claim 8, wherein:

the at least two features comprise tungsten covered by a silicon nitride or titanium nitride hard mask material;

the filler feature comprises tungsten; and

the sidewall spacers comprise silicon oxide.

10. The method of claim 9, wherein the at least two features are retained in a completed device as portions of upper electrodes.

11. The method of claim 1, wherein:

the at least two features comprise a first electrically insulating material;

the filler feature comprises the first electrically insulating material; and

the sidewall spacers comprise a second electrically insulating material different from the first electrically insulating material.

12. The method of claim 11, wherein:

the at least two features comprise silicon oxide;

the filler feature comprises silicon oxide; and

the sidewall spacers comprise silicon nitride.

13. The method of claim 12, further comprises removing the at least two features and the filler feature after the step of etching the at least one device layer.

14. The method of claim 1, wherein the step of etching the at least one device layer comprises etching at least one semiconductor device layer to form a plurality of pillar shaped devices.

15. The method of claim 14, wherein the plurality of pillar shaped devices comprise a plurality of diode containing nonvolatile memory cells.

16. The method of claim 14, wherein the at least two features have a substantially cylindrical shape and the filler feature has a substantially rectangular or square shape with concave sidewalls.

17. A method of making a pillar shaped nonvolatile memory device array, comprising:

forming a plurality of bottom electrodes over a substrate;

forming at least one semiconductor device layer over the plurality of bottom electrodes;

forming a plurality of spaced apart features over the at least one semiconductor device layer;

forming sidewall spacers on the plurality of spaced apart features;

forming a filler film over and between the plurality of spaced apart features;

planarizing the filler film to expose upper portions of the plurality of spaced apart features and upper portions of the sidewall spacers to leave a plurality of filler features located between the sidewall spacers;

selectively removing the sidewall spacers to leave the plurality of spaced apart features and the plurality of filler features spaced apart from each other;

etching the at least one semiconductor device layer using the plurality of spaced apart features and the plurality of filler features as a mask to form a plurality of pillar shaped diode containing nonvolatile memory cells; and

forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells.

18. The method of claim 17, wherein:

the plurality of spaced apart features and the plurality of filler features comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing comprises selectively etching the second material of the sidewall spacers without substantially removing the first material.

19. The method of claim 17, wherein:

the plurality of spaced apart features comprise a first material, and the plurality of filler features comprise a second material and the sidewall spacers comprise a third material different from the first and the second material; and

the step of selectively removing comprises selectively etching the third material of the sidewall spacers without substantially removing the first or the second material.

20. The method of claim 17, wherein:

the plurality of spaced apart features comprise tungsten covered by a silicon nitride or titanium nitride hard mask material;

the plurality of filler features comprise tungsten; and

the sidewall spacers comprise silicon oxide.

21. The method of claim 20, wherein the plurality of spaced apart features comprise at least a portion of the upper electrodes.

22. The method of claim 17, wherein:

the plurality of spaced apart features comprise silicon oxide;

the plurality of filler features comprise silicon oxide; and

the sidewall spacers comprise silicon nitride.

23. The method of claim 22, further comprises removing the plurality of spaced apart features and the plurality of filler features after the step of etching the at least one semiconductor device layer.

24. The method of claim 17, wherein each of the plurality of spaced apart features has a substantially cylindrical shape and each of the plurality of filler features has a substantially rectangular or square shape with concave sidewalls.

25. The method of claim 17, further comprising removing the filler film from areas outside of the device array boundary.

26. The method of claim 25, further comprising:

providing alignment edge features adjacent to a device array boundary, wherein the alignment edge features have a larger size than the plurality of spaced apart features;

after the step of planarizing the filler film, forming a photoresist layer over the plurality of filler features and over the plurality of spaced apart features;

exposing the photoresist layer using the alignment edge features during alignement;

patterning the exposed photoresist layer to form a photoresist pattern covering a device array area; and

etching the filler film in areas outside of the device array boundary that are not covered by the photoresist pattern.

27. The method of claim 17, wherein the step of forming sidewall spacers comprises forming the sidewall spacers on the plurality of features, such that the sidewalls spacers on adjacent features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers.