MEMORY HAVING IMPROVED READ CAPABILITY

• US 20090157946A1
• Filed: 12/12/2007
• Published: 06/18/2009
• Est. Priority Date: 12/12/2007
• Status: Abandoned Application

• Current Assignee: Greenliant LLC
• Original Assignee: Greenliant LLC
• Inventors: Arya, Siamak
• Application Number:
  US11/954,577
• Publication Number:
  US 20090157946A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency.

Claims

1. A memory comprising:

a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller, and having a first bus for receiving address signals from a host device;

a second bus for interfacing with a RAM memory; and

a third bus for interfacing with a NAND memory;

a volatile RAM memory connected to said second bus;

a NAND memory connected to said third bus;

said controller for receiving commands and a first address from said first bus, and for mapping said first address to a second address in said NAND memory and for operating said NAND memory in response thereto, with said RAM memory serving as cache for data to or from the NAND memory;

said controller for maintaining data coherence between the data stored in the RAM memory as cache and the data in the NAND memory

a first buffer for storing data read from the NAND memory and for storing in the RAM memory; and

a second buffer for storing data read from the RAM memory and for storing in the NAND memory.

2. The memory of claim 1 wherein said controller further comprising program code stored in said non-volatile memory for mapping said first address to a second address in said NAND memory and for operating said NAND memory in response thereto, with said RAM memory serving as cache for data to or from the second address in the NAND memory and further wherein said program code for maintaining data coherence between the data stored in the RAM as cache and the data at the second address in the NAND memory.

3. The memory of claim 1, wherein data read from the NAND memory or written to the NAND memory is read or written in a set density.

4. The memory of claim 3 wherein said set density is a page.

5. The memory of claim 3 wherein the first buffer is said set density, and wherein said second buffer is said density.

6. The memory of claim 3 wherein the first buffer is a multiple of said set density, and wherein said second buffer is said multiple of said set density.

7. The memory of claim 6, wherein said memory controller for operating said first buffer by reading said NAND memory and storing said set density of data from said NAND memory in one of said multiple of said set density of said first buffer, while simultaneously, reading another of said multiple of said set density of said first buffer and storing said set density of data in said RAM memory.

8. A memory device comprising:

a memory controller having a first bus for interfacing with a host device for receiving address signals therefrom;

a NAND memory connected to the memory controller; and

a RAM memory connected to the memory controller, said RAM memory acting as cache for said NAND memory,

a first buffer connected to the NAND memory for storing data read therefrom, and connected to the RAM memory for writing data thereto; and

a second buffer connected to the RAM memory for storing data read therefrom and connected to the NAND memory for writing data thereto.

9. The memory device of claim 8 wherein said memory controller further comprising:

a read/miss logic circuit for determining whether the data at the address specified by the address signals from the host device is

a) stored in the RAM memory and is to be supplied to the host device in lieu of reading from the NAND memory;

or

b) not stored in the RAM memory and is to be first read from the NAND memory and stored in the first buffer and then stored in the RAM memory prior to being supplied to the host device, provided that the RAM memory has over-writable space for the storage of the data from the first buffer;

or

c) not stored in the RAM memory and is to be first read from the NAND memory and stored in the first buffer and then stored in the RAM memory prior to being supplied to the host device, with a portion of the RAM memory preserved by writing said portion into the second buffer, prior to the contents from the first buffer is stored in the RAM memory.

10. The memory device of claim 9 wherein the data at the address specified by the host device is stored among a page of data on the NAND device, wherein the page of data contains contents specified by the host device and other contents, and wherein the page of data is read from the NAND memory and stored in the RAM memory.

11. The memory device of claim 8, wherein data read from the NAND memory or written to the NAND memory is read or written in a set density.

12. The memory device of claim 11 wherein said set density is a page.

13. The memory device of claim 11 wherein the first buffer is said set density, and wherein said second buffer is said density.

14. The memory device of claim 11 wherein the first buffer is a multiple of said set density, and wherein said second buffer is said multiple of said set density.

15. The memory device of claim 14, wherein said memory controller for operating said first buffer by reading said NAND memory and storing said set density of data from said NAND memory in one of said multiple of said set density of said first buffer, while simultaneously, reading another of said multiple of said set density of said first buffer and storing said set density of data in said RAM memory.

16. A method of operating a memory controller having a first bus for interfacing with a host device for receiving a first read operation having a first address signal therefrom, a NAND memory connected to the memory controller;

a RAM memory connected to the memory controller, with said RAM memory acting as cache for said NAND memory, a first buffer between said NAND memory and said RAM memory, and a second buffer between said NAND memory and said RAM memory, and wherein the memory controller for operating the NAND memory, the RAM memory and the first and second buffers, said method comprising;

receiving the first address signal;

determining if the data specified by the first address signal is stored in the RAM memory; and

a) if so, supplying the data from the RAM memory to the host device in lieu of reading from the NAND memory;

or

b) if not, determining if the RAM memory has sufficient over-writable memory space to store a page of contents read from the NAND memory into the first buffer, wherein the page of contents include the data specified by the first address signal,

i) if so, reading the page of contents from the NAND memory into the first buffer, wherein said page of contents includes data associated with the first address signal, and storing the page of contents in the RAM memory, and supplying the data associated with the first address signal from the RAM memory to the host device;

ii) if not, clearing sufficient over-writable memory space in the RAM memory by storing at least a page of data from the RAM memory into the second buffer;

reading the page of contents from the NAND memory into the first buffer, wherein said page of contents includes data associated with the first address signal, and storing the page of contents in the RAM memory, and supplying the data associated with the first address signal from the RAM memory to the host device.

17. The method of claim 16 wherein the step of (b)(i) further comprises

(b)(i)(a) reading the page of contents from the NAND memory into a first portion of the first buffer, wherein said page of contents includes data associated with the first address signal;

and

(b)(i)(b) storing the page of contents from the first portion of the first buffer in the RAM memory and supplying the data associated with the first address signal from the RAM memory to the host device, while simultaneously reading a second page of contents from the NAND memory into a second portion of the first buffer, in response to a second read operation having a second address signal, wherein the second page of contents includes data associated with the second address signal.

18. The method of claim 16 wherein the step of (b)(ii) further comprises

(b)(i)(a) reading the page of contents from the NAND memory into a first portion of the first buffer, wherein said page of contents includes data associated with the first address signal, while simultaneously clearing sufficient over-writable memory space in the RAM memory by storing at least a page of data from the RAM memory into the second buffer;

and

(b)(i)(b) storing the page of contents from the first portion of the first buffer in the RAM memory and supplying the data associated with the first address signal from the RAM memory to the host device, while simultaneously reading a second page of contents from the NAND memory into a second portion of the first buffer, in response to a second read operation having a second address signal, wherein the second page of contents includes data associated with the second address signal.

19. The method of claim 16 wherein the step of (b)(ii) further comprises:

writing the contents in the second buffer cleared from the RAM memory into the NAND memory.

20. The method of claim 19 wherein said writing step occurs after supplying the data associated with the first address signal from the RAM memory to the host device.

21. The method of claim 16 wherein in response to a subsequent read operation having a second address signal, said method comprises:

determining if the data associated with the second address signal is stored in the second buffer; and

if so, reading said data in the second buffer into the RAM memory and supplying to the host device.

22. The method of claim 16 wherein in response to a subsequent read operation having a second address signal, said method comprises:

determining if the data associated with the second address signal is stored in the second buffer; and

if so, writing the contents in the second buffer cleared from the RAM memory, including the data associated with the second address signal, into the NAND memory; and

reading a page of contents including the data associated with the second address signal from the NAND memory into the first buffer and into the RAM memory and supplying to the host device.