EFFICIENT DATA STORAGE IN MULTI-PLANE MEMORY DEVICES

• US 20090157964A1
• Filed: 12/11/2008
• Published: 06/18/2009
• Est. Priority Date: 12/16/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sokolov, Dotan, Gurgi, Eyal, Kasorla, Yoav
• Granted Patent: US 8,456,905 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays.

Claims

1. A method for data storage, comprising:

initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays;

rearranging the initially-stored data pages in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number; and

reading the rearranged data pages from the second number of the memory arrays.

2. The method according to claim 1, wherein reading the rearranged data pages comprises reading a given data page and one or more neighboring data pages from the second number of the memory arrays and canceling cross-coupling interference in the given data page responsively to the read neighboring data pages.

3. The method according to claim 2, wherein reading the rearranged data pages comprises caching the read data pages in a cache memory such that both the given data page and the neighboring data pages are cached in the cache memory at a given time, and wherein canceling the cross-coupling interference comprises canceling the interference using the cached given data page and neighboring data pages.

4. The method according to claim 1, wherein the second number of the memory arrays comprises a single memory array.

5. The method according to claim 1, wherein the second number of the memory arrays comprises two or more memory arrays, and wherein rearranging the initially-stored data pages comprises storing the successive data pages in alternation in the second number of the memory arrays.

6. The method according to claim 1, wherein rearranging the initially-stored data pages comprises rearranging the initially-stored data pages so as to store the successive data pages in a third number of the memory arrays, which is smaller than the first number and larger than the second number, and rearranging the data pages stored in the third number of the memory arrays so as to store the successive data pages in the second number of the memory arrays.

7. The method according to claim 1, wherein rearranging the initially-stored data pages comprises defining multiple groups of the memory arrays, each group having the second number of the memory arrays, and storing respective subsets of the successive data pages in the groups.

8. The method according to claim 7, wherein storing the subsets in the groups comprises sending multi-plane write commands, each command specifying storage of the second number of the data pages in each of the groups.

9. The method according to claim 1, wherein initially storing the sequence comprises sending multi-plane write commands, each command specifying storage of the first number of the data pages in the first number of the memory arrays.

10. The method according to claim 1, wherein initially storing the sequence comprises sending an acknowledgement indication responsively to a successful completion of initially-storing the sequence, irrespective of rearrangement of the initially-stored data pages.

11. The method according to claim 1, wherein rearranging the initially-stored data pages comprises rearranging the data pages during an idle period in which no memory access operations are performed.

12. The method according to claim 1, wherein each of the memory arrays comprises a plurality of analog memory cells, wherein initially storing the sequence comprises programming the memory cells in the first number of the memory arrays using first programming parameters, and wherein rearranging the data pages comprises programming the memory cells in the second number of the memory arrays using second programming parameters, different from the first programming parameters.

13. The method according to claim 12, wherein programming the memory cells using the first programming parameters comprises programming the memory cells to assume a first number of programming levels, and wherein programming the memory cells using the second programming parameters comprises programming the memory cells to assume a second number of programming levels, larger than the first number.

14. The method according to claim 12, wherein programming the memory cells using the first programming parameters comprises applying to the memory cells a first sequence of programming pulses whose amplitude increases incrementally by a first step size, and wherein programming the memory cells using the second programming parameters comprises applying to the memory cells a second sequence of programming pulses whose amplitude increases incrementally by a second step size, smaller than the first step size.

15. The method according to claim 1, wherein reading the rearranged data pages comprises:

receiving a request from a host to retrieve one or more requested data pages in the sequence;

responsively to the request, reading from the second number of the memory arrays one or more non-requested data pages in the sequence, which were not requested by the host, as well as the requested data pages;

caching the read requested and non-requested data pages; and

canceling cross-coupling interference in at least one of the requested data pages using the cached requested and non-requested data pages.

16. The method according to claim 1, wherein initially storing the data pages comprises storing the data pages in a Dynamic Random Access Memory (DRAM), and wherein rearranging the initially-stored data pages comprises copying the data pages from the DRAM to a non-volatile memory.

17. The method according to claim 1, wherein the memory cells in the second number of the memory arrays are arranged along multiple word lines, and wherein rearranging the initially-stored data pages comprises storing the data pages in an ascending order of the word lines and in a reverse order of the sequence.

18. A method for data storage, comprising:

storing a sequence of data pages in a memory;

receiving a series of requests from a host to sequentially retrieve the stored data pages from the memory;

responsively to a given request received at a given time, reading from the memory one or more non-requested data pages in the sequence, which were not yet requested by the host at the given time, as well as reading one or more requested data pages specified in the given request;

caching the read requested and non-requested data pages; and

canceling cross-coupling interference in at least one of the requested data pages using the cached requested and non-requested data pages.

19. A data storage apparatus, comprising:

a memory, which comprises multiple memory arrays; and

circuitry, which is coupled to initially store a sequence of data pages in the memory such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays, to rearrange the initially-stored data pages in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number, and to read the rearranged data pages from the second number of the memory arrays.

20. The apparatus according to claim 19, wherein the circuitry is coupled to read a given data page and one or more neighboring data pages from the second number of the memory arrays, and to cancel cross-coupling interference in the given data page responsively to the read neighboring data pages.

21. The apparatus according to claim 20, and comprising a cache memory, wherein the circuitry is coupled to cache the read data pages in the cache memory such that both the given data page and the neighboring data pages are cached in the cache memory at a given time, and to cancel the interference using the cached given data page and neighboring data pages.

22. The apparatus according to claim 19, wherein the second number of the memory arrays comprises a single memory array.

23. The apparatus according to claim 19, wherein the second number of the memory arrays comprises two or more memory arrays, and wherein the circuitry is coupled to rearrange the initially-stored data pages by storing the successive data pages in alternation in the second number of the memory arrays.

24. The apparatus according to claim 19, wherein the circuitry is coupled to rearrange the initially-stored data pages so as to store the successive data pages in a third number of the memory arrays, which is smaller than the first number and larger than the second number, and to rearrange the data pages stored in the third number of the memory arrays so as to store the successive data pages in the second number of the memory arrays.

25. The apparatus according to claim 19, wherein the circuitry is coupled to define multiple groups of the memory arrays, each group having the second number of the memory arrays, and to rearrange the initially-stored data pages by storing respective subsets of the successive data pages in the groups.

26. The apparatus according to claim 25, wherein the circuitry is coupled to store the subsets in the groups using multi-plane write commands, each command specifying storage of the second number of the data pages in each of the groups.

27. The apparatus according to claim 19, wherein the circuitry is coupled to initially store the sequence using multi-plane write commands, each command specifying storage of the first number of the data pages in the first number of the memory arrays.

28. The apparatus according to claim 19, wherein the circuitry is coupled to send an acknowledgement indication responsively to a successful completion of initially-storing the sequence, irrespective of rearrangement of the initially-stored data pages.

29. The apparatus according to claim 19, wherein the circuitry is coupled to rearrange the data pages during an idle period in which no memory access operations are performed.

30. The apparatus according to claim 19, wherein each of the memory arrays comprises a plurality of analog memory cells, and wherein the circuitry is coupled to initially store the sequence by programming the memory cells in the first number of the memory arrays using first programming parameters, and to rearrange the data pages by programming the memory cells in the second number of the memory arrays using second programming parameters, different from the first programming parameters.

31. The apparatus according to claim 30, wherein the circuitry is coupled to program the memory cells using the first programming parameters by programming the memory cells to assume a first number of programming levels, and to program the memory cells using the second programming parameters by programming the memory cells to assume a second number of programming levels, larger than the first number.

32. The apparatus according to claim 30, wherein the circuitry is coupled to program the memory cells using the first programming parameters by applying to the memory cells a first sequence of programming pulses whose amplitude increases incrementally by a first step size, and to program the memory cells using the second programming parameters by applying to the memory cells a second sequence of programming pulses whose amplitude increases incrementally by a second step size, smaller than the first step size.

33. The apparatus according to claim 19, wherein the circuitry is coupled to receive a request from a host to retrieve one or more requested data pages in the sequence, to read from the second number of the memory arrays, responsively to the request, one or more non-requested data pages in the sequence that were not requested by the host in addition to reading the requested data pages, to cache the read requested and non-requested data pages, and to cancel cross-coupling interference in at least one of the requested data pages using the cached requested and non-requested data pages.

34. The apparatus according to claim 19, wherein the memory comprises a Dynamic Random Access Memory (DRAM) and a non-volatile memory, and wherein the circuitry is coupled to initially store the data pages in the DRAM and to rearrange the initially-stored data pages by copying the data pages from the DRAM to the non-volatile memory.

35. The apparatus according to claim 19, wherein the memory cells in the second number of the memory arrays are arranged along multiple word lines, and wherein the circuitry is coupled to rearrange the initially-stored data pages by storing the data pages in an ascending order of the word lines and in a reverse order of the sequence.

36. A data storage apparatus, comprising:

a memory; and

a processor, which is coupled to store a sequence of data pages in a memory, to receive a series of requests from a host to sequentially retrieve the stored data pages from the memory, to read from the memory, responsively to a given request received at a given time, one or more non-requested data pages in the sequence that were not yet requested by the host at the given time, as well as reading one or more requested data pages specified in the given request, to cache the read requested and non-requested data pages, and to cancel cross-coupling interference in at least one of the requested data pages using the cached requested and non-requested data pages.

37. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple memory arrays; and

a processor, which is coupled to initially store a sequence of data pages in the memory such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays, to cause the memory to rearrange the initially-stored data pages in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number, and to read the rearranged data pages from the second number of the memory arrays.