Method and Apparatus for Performing Improved Group Instructions

• US 20090158012A1
• Filed: 10/29/2007
• Published: 06/18/2009
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Granted Patent: US 7,849,291 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 : Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 : Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Claims

1. A processor comprising:

a virtual memory addressing unit;

a data path;

a register file comprising a plurality of registers coupled to the data path;

an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path.

2. The processor of claim 1 wherein the group floating-point operations involve operating on at least two of the multiple floating-point operands in parallel.

3. The processor of claim 1 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of more than one of the plurality of registers.

4. The processor of claim 1 wherein the group floating-point operations involve operating on multiple floating-point operands stored in partitioned fields of only one of the plurality of registers.

5. The processor of claim 4 wherein the group floating-point operations include at least one group square root operation that performs a square root computation on each of the multiple floating-point operands.

6. The processor of claim 5 wherein each of the multiple floating-point operands for the at least one group square root operation represents a double-precision floating-point value.

7. The processor of claim 5 wherein each of the multiple floating-point operands for the at least one group square root operation represents a single-precision floating-point value.

8. The processor of claim 1 wherein the catenated results are returned to a register in the plurality of registers.

9. The processor of claim 1 wherein the plurality of registers in the register file are general purpose registers that can be used as operand and result registers for group floating-point operations.

10. The processor of claim 1 wherein floating-point values can be stored in registers in a format conforming to IEEE standard 754.

11. The processor of claim 1 wherein the execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

12. The processor of claim 1 wherein the execution unit is capable of generating and handling floating-point arithmetic exceptions for group floating-point operations.

13. The processor of claim 1 wherein the execution unit is also capable of executing group integer operations in which multiple integer operands stored in partitioned fields of registers are operated on to produce a catenated result.

14. The processor of claim 13 wherein the group integer operations involve operating on at least two of the multiple integer operands in parallel.

15. The processor of claim 13 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of more than one of the plurality of registers.

16. The processor of claim 13 wherein the group integer operations involve operating on multiple integer operands stored in partitioned fields of only one of the plurality of registers.

17. The processor of claim 13 wherein:

the group floating-point operations include group add, group subtract, group compare, group multiply and group divide arithmetic operations that operate on catenated floating-point data; and

the group integer operations include group add, group subtract, group compare and group multiply arithmetic operations that operate on catenated integer data.

18. The processor of claim 13 wherein the execution unit is capable of generating and handling fixed-point arithmetic exceptions for group integer operations.

19. The processor of claim 1 wherein the execution unit is capable of performing group integer operations on integer data of more than one precision.

20. The processor of claim 19 wherein the group integer operations include instructions that perform arithmetic operations on integer data having an elemental width of 8 bits, instructions that perform arithmetic operations on integer data having an elemental width of 16 bits and instructions that perform arithmetic operations on integer data having an elemental width of 32 bits.

21. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations including operations that copy, operations that shift, operations that rearrange and operations that resize catenated integer data stored in a register and return catenated results of the operation.

22. The processor of claim 21 wherein the catenated results of the group data handling operation are returned to a register.

23. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations on integer data having a symbol width of 8 bits, group data handling operations on integer data having a symbol width of 16 bits, and group data handling operations on integer data having a symbol width of 32 bits.

24. The processor of claim 1 wherein the execution unit is capable of performing group data handling operations comprising:

a shift left operation that shifts bits of individual data elements catenated in an operand register to the left and clears empty low order bits of the individual data elements to zero;

a first shift right operation that shifts bits of individual data elements catenated in an operand register to the right and fills empty high order bits of the individual data elements with a value equal to a value stored in a sign bit of the individual data element; and

a second shift right operation that shifts bits of individual data elements catenated in an operand register to the right and clears empty high order bits of the individual data elements to zero.

25. The processor of claim 1 further comprising an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path.

26. The processor of claim 1 further comprising:

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path.

27. The processor of claim 1 wherein the execution unit is capable of executing a Galois field operation.

28. The processor of claim 1 wherein the execution unit is configurable to execute a plurality of instruction streams in parallel from a plurality of threads;

and wherein the processor comprises a register file associated with each thread executing in parallel on the execution unit to support processing of the plurality of threads.

29. The processor of claim 28 wherein the execution unit executes instructions from said plurality of instruction streams in a round-robin manner.

30. The processor of claim 29 wherein the processor ensures only one thread from the plurality of threads can handle an exception at any given time.

31. The processor of claim 1 wherein the virtual memory addressing unit is capable of supporting a linear virtual address space, a segmented virtual address space and page mapping from virtual addresses to physical addresses.

32. The processor of claim 1 further comprising a plurality of memory management registers.

33. The processor of claim 1 wherein the virtual memory addressing unit is part of a general purpose processor architecture capable of generating and handling virtual memory exceptions.

34. The processor of claim 1 further comprising an instruction pipeline that has a front stage and a back stage that is decoupled from the front stage by a memory buffer.

35. The processor of claim 34 wherein the front stage handles address calculation, memory load and branch operations and the back stage handles data calculation and memory store operations.

36. The processor of claim 1 further comprising an instruction pipeline having an address calculation stage, an execution stage and a memory buffer between the address calculation stage and execution stage to delay execution of instructions not ready.

37. The processor of claim 1 wherein the register file comprises a plurality of registers configurable to receive and store 128 bits of catenated data from the data path and communicate the 128 bits of catenated data to the data path, wherein the elemental width of the catenated data may be any one of the following types:

1-bit Boolean type;

8-bit, 16-bit, 32-bit and 64-bit integer type; and

32-bit floating-point type.

38. The processor of claim 1 wherein the execution unit is capable of performing parallel operations on catenated data of a total aggregate width of 128 bits.

39. A programmable processor capable of operation independent of another host processor, the programmable processor comprising:

a virtual memory addressing unit;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file comprising a plurality of registers coupled to the data path;

a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer and group floating-point operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision.

40. The processor of claim 39 wherein the multi-precision execution unit comprises a plurality of functional units.

41. The processor of claim 40 wherein the plurality of functional units further comprises a first functional unit that performs arithmetic operations and a second functional unit that performs data handling operations.

42. The processor of claim 41 wherein the first functional unit performs floating point arithmetic operations.

43. The processor of claim 42 wherein the first functional unit further performs integer arithmetic operations.

44. The processor of claim 40 wherein the multi-precision execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

45. The processor of claim 40 wherein the multi-precision execution unit is capable of performing group data handling operations on integer data of more than one precision.

46. The processor of claim 40 wherein the register file comprises a plurality of registers that can be used as operand and result registers for group floating-point and group integer operations.

47. The processor of claim 40 wherein the group floating-point operations involve operating on at least two of the multiple floating-point operands in parallel.

48. The processor of claim 39 wherein the multi-precision execution unit is capable of performing parallel operations on catenated data of a total aggregate width of 128 bits.

49. The processor of claim 39 wherein for at least some group integer and group floating-point operations the catenated results are returned to a register in the plurality of registers that is an operand register used for the operation.

50. A programmable processor capable of operation independent of another host processor, the programmable processor comprising:

a virtual memory addressing unit;

a data path;

an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file comprising a plurality of registers coupled to the data path, the plurality of registers configurable to receive and store catenated data from the data path and communicate the catenated data to the data path, wherein the elemental width of the catenated data may be any one of the following types;

8-bit, 16-bit, 32-bit and 64-bit integer type and 32-bit floating-point type;

a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer, group floating-point and group data handling operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on in parallel to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision.

51. The processor of claim 50 wherein the multi-precision execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

52. The processor of claim 50 wherein the register file comprises a plurality of registers that can be used as operand and result registers for group floating-point and group integer operations.

53. The processor of claim 52 wherein the multi-precision execution unit comprises a plurality of functional units.

54. The processor of claim 53 wherein:

the group floating-point operations include group add, group subtract, group compare and group multiply arithmetic operations that operate on catenated floating-point data;

the group integer operations include group add, group subtract, group compare and group multiply arithmetic operations that operate on catenated integer data; and

the group data handling operations include operations that copy, operations that shift and operations that resize catenated integer data.