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Method and Apparatus Implementing a Minimal Area Consumption Multiple Addend Floating Point Summation Function in a Vector Microprocessor

  • US 20090158013A1
  • Filed: 12/13/2007
  • Published: 06/18/2009
  • Est. Priority Date: 12/13/2007
  • Status: Active Grant
First Claim
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1. A method for computing an arithmetic result of more than two operands, comprising:

  • in response to receiving a multiple operand instruction, transferring more than two operands from a register file to a vector unit, wherein each operand is transferred to a respective one of a plurality of processing lanes of the vector unit;

    transferring each of the more than two operands from respective processing lanes of the vector unit to a dot product unit; and

    computing an arithmetic result of the more than two operands in the dot product unit.

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