Method and Apparatus Implementing a Minimal Area Consumption Multiple Addend Floating Point Summation Function in a Vector Microprocessor

• US 20090158013A1
• Filed: 12/13/2007
• Published: 06/18/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam J., Tubbs, Matthew R.
• Granted Patent: US 8,239,439 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may be transferred from the vector unit to a dot product unit wherein an arithmetic operation using the more than two operands may be performed.

Claims

1. A method for computing an arithmetic result of more than two operands, comprising:

in response to receiving a multiple operand instruction, transferring more than two operands from a register file to a vector unit, wherein each operand is transferred to a respective one of a plurality of processing lanes of the vector unit;

transferring each of the more than two operands from respective processing lanes of the vector unit to a dot product unit; and

computing an arithmetic result of the more than two operands in the dot product unit.

2. The method of claim 1, wherein the more than two operands are received from one or more registers in a register file.

3. The method of claim 2, wherein each register in the register file comprises a plurality of operands.

4. The method of claim 2, further comprising transferring the more than two operands from the register file to an operand reordering device, the operand reordering device being configured to transfer each operand to a respective one of the plurality of processing lanes of the vector unit.

5. The method of claim 3, wherein operand reordering device is further configured to transfer one or more predetermined values to each processing lane of the vector unit.

6. The method of claim 1, wherein each processing lane of the vector unit comprises an adder, a multiplier, an aligner, and a normalizer.

7. The method of claim 1, wherein the dot product unit comprises an adder configured to determine the arithmetic result.

8. The method of claim 1, wherein the dot product unit comprises at least one aligner and a normalizer.

9. The method of claim 7, wherein determining the arithmetic result comprises determining a sum of the more than two operands.

10. The method of claim 7, wherein determining the arithmetic result comprises determining a difference between a first operand and a second operand.

11. A method for computing a sum of three operands, comprising:

in response to receiving a three addend instruction, transferring three operands from a register file to a vector unit, wherein each of the three operands are transferred to a respective one of a plurality of processing lanes of the vector unit;

transferring each of the three operands from respective processing lanes of the vector unit to a dot product unit; and

computing a sum of the three operands in the dot product unit.

12. The method of claim 11, wherein the three operands are received from one or more registers in a register file.

13. The method of claim 12, further comprising transferring the more than two operands from the register file to an operand reordering device, the operand reordering device being configured to transfer each of the three operands to a respective one of the plurality of processing lanes of the vector unit.

14. The method of claim 11, wherein each vector processing lane comprises an adder, a multiplier, an aligner, and a normalizer.

15. The method of claim 11, wherein the dot product unit comprises an adder configured to computer a sum of the three operands.

16. A system comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:

a register file comprising a plurality of registers, each register comprising a plurality of operands;

a vector unit comprising a plurality of vector processing lanes and configured to receive more than two operands, each operand being received in a respective one of a plurality of processing lanes of the vector unit, and transfer the more than two operands to a dot product unit; and

the dot product unit configured to receive each of the more than two operands from respective processing lanes of the vector unit and compute an arithmetic result of the more than two operands.

17. The system of claim 16, further comprising an operand reordering device configured to receive the more than two operands from the register file and transfer each operand to a respective one of the plurality of processing lanes of the vector unit.

18. The system of claim 16, wherein each register of the register file comprises four operands.

19. The system of claim 16, wherein each processing lane of the vector unit comprises an adder, a multiplier, an aligner, and a normalizer.

20. The system of claim 16, wherein the dot product unit comprises an adder configured to compute the arithmetic result.

21. The system of claim 16, wherein the dot product unit comprises at least one aligner and a normalizer.

22. The system of claim 16, wherein computing the arithmetic result comprises computing a sum of the more than two operands.

23. The system of claim 16, wherein computing the arithmetic result comprises determining a difference between a first operand and a second operand.