VITERBI DECODING APPARATUS AND METHOD

• US 20090158131A1
• Filed: 08/08/2008
• Published: 06/18/2009
• Est. Priority Date: 12/13/2007
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kang, Kyu-Min, Park, Kwang Roh, Choi, Sang Sung, CHOI, Sung Woo
• Application Number:
  US12/188,416
• Publication Number:
  US 20090158131A1
• Time in Patent Office: Days
• US Class Current: 714/795
• CPC Class Codes: H03M 13/3972 using sliding window techniques or parallel windows
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6356 by repetition or insertion of dummy data, i.e. rate reduction
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A Viterbi decoding apparatus receives a plurality of block data in time order, and transmits a block data group including the plurality of block data. Then, the Viterbi decoding apparatus applies a Viterbi decoding algorithm to the block data group and outputs some block data of the block data group. In this way, it is possible to provide a Viterbi decoding apparatus that can operate at a high speed and improve a data transmission rate.

Claims

1. A Viterbi decoding method comprising:

receiving a plurality of block data in time order;

transmitting a first block data group including the plurality of block data;

applying a Viterbi decoding algorithm to the first block data group and outputting some block data of the first block data group;

receiving a plurality of additional block data connected with the plurality of block data in time order;

transmitting a second block data group including the plurality of additional block data and some block data of the first block data group; and

applying the Viterbi decoding algorithm to the second block data group and outputting some block data of the second block data group.

2. The Viterbi decoding method of claim 1,

wherein the receiving of the plurality of block data includes

receiving an even number of block data in time order, and

the receiving of the plurality of additional block data includes

receiving an even number of additional block data in time order.

3. The Viterbi decoding method of claim 2,

wherein the even number of block data is four block data,

the even number of additional block data is two additional block data, and

the second block data group includes two of the four block data and the two additional block data.

4. The Viterbi decoding method of claim 3, wherein the second block data group includes two of the four block data that are received late in time order.

5. The Viterbi decoding method of claim 3,

wherein the outputting of some block data of the first block data group includes

outputting the second block data and third block data of the first block data group that are received in time order.

6. The Viterbi decoding method of claim 3,

wherein the outputting of some block data of the second block data group includes

outputting the second block data and the third block data of the second block data group that are received in time order.

7. The Viterbi decoding method of claim 1, wherein the Viterbi decoding algorithm is a block processing Viterbi decoding algorithm.

8. A Viterbi decoding apparatus that receives data from a depuncturer including two memory buffers and outputting the data from the depuncturer using output clocks which is equal to or higher than input clocks, and performs decoding, the apparatus comprising:

a distributor that receives a plurality of bits from the depuncturer, and distributes the received plurality of bits to each block data unit;

a plurality of memory banks that receive block data corresponding to some of the plurality of bits from the distributor in a predetermined order, and store the received block data;

a plurality of switches that are connected to some of the plurality of memory banks, and output the block data stored in one of the connected memory banks; and

a plurality of decoders that are connected to some of the plurality of switches, receive a plurality of block data from the connected switches, process the plurality of block data according to a Viterbi decoding algorithm, and output some of the plurality of block data.

9. The Viterbi decoding apparatus of claim 8, wherein some or all of the plurality of decoders are used according to the number of bits simultaneously input to the distributor.

10. The Viterbi decoding apparatus of claim 9,

wherein the plurality of memory banks are an even number of memory banks, the plurality of switches are an even number of switches, and

odd-numbered switches of the even number of switches are connected in parallel to odd-numbered memory banks of the even number of memory banks, and even-numbered switches of the even number of switches are connected in parallel to even-numbered memory banks of the even number of memory banks.

11. The Viterbi decoding apparatus of claim 8, wherein the plurality of decoders are sliding block Viterbi decoders using a block processing Viterbi decoding method.

12. The Viterbi decoding apparatus of claim 8,

wherein the plurality of memory banks include eight memory banks,

the plurality of switches include eight switches, and

the plurality of decoders include two decoders.

13. The Viterbi decoding apparatus of claim 12, wherein each of the two decoders has transmission capacity that is half the maximum transmission capacity of the Viterbi decoding apparatus.