TEST PATTERN FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE TEST PATTERN

• US 20090159883A1
• Filed: 12/14/2008
• Published: 06/25/2009
• Est. Priority Date: 12/24/2007
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Lee, Choon-Ho
• Application Number:
  US12/334,497
• Publication Number:
  US 20090159883A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test pattern for a semiconductor device and a method for forming the test pattern that can determine the degree of over etching of contact holes and obviate the need to perform a physical analysis using SEM, FIB or the like after the wafer is destroyed.

Claims

1. An apparatus comprising:

a semiconductor substrate having a plurality of regions, at least one region having a trench formed therein;

a lower conductive layer formed at the regions, wherein the at least one region has a lower conductive layer formed in the semiconductor substrate;

an interlayer insulating layer formed over the semiconductor substrate including each lower conductive layer;

a plurality of contact plugs formed spaced apart in the interlayer insulating layer and connected electrically to a respective lower conductive layer; and

an upper conductive layer formed over the interlayer insulating layer and electrically connected to a respective lower conductive layer through the contact plugs.

2. The apparatus of claim 1, wherein the plurality of regions comprises a first region and a second region such that the second region has the trench.

3. The apparatus of claim 1, wherein the second region corresponds to a common source wire region of a device.

4. The apparatus of claim 3, wherein the device comprises a flash memory device.

5. The apparatus of claim 1, wherein the plurality of regions comprises a first region, a second region and a third region such that the second region and the third region have the trench.

6. The apparatus of claim 5, wherein the first region is formed at a first height, the second region is formed at a second height lower than the first height and the third region is formed at a third height lower than the second height and the first height.

7. The apparatus of claim 5, wherein at least one of the second region and the third region corresponds to a common source wire region of a device.

8. The apparatus of claim 7, wherein the device comprises a flash memory device.

9. A method comprising:

providing a semiconductor substrate having a plurality of regions; and

then

forming a trench in at least one of the regions; and

then

forming a lower conductive layer at the regions, wherein the at least one of the regions has a lower conductive layer formed in the semiconductor substrate; and

then

forming an interlayer insulating layer over the semiconductor substrate including each lower conductive layer; and

then

forming a plurality of contact holes spaced apart in the interlayer insulating layer exposing the a respective lower conductive layer; and

then

forming a contact plug spaced apart in the contact holes and connected electrically to a respective lower conductive layer; and

then

forming an upper conductive layer over the interlayer insulating layer and electrically connected to a respective lower conductive layer through the contact plug.

10. The method of claim 9, wherein the plurality of regions comprises a first region and a second region.

11. The method of claim 10, wherein forming the trench comprises forming a trench in the second region.

12. The method of claim 11, wherein the second region corresponds to a common source wire region of a device.

13. The method of claim 12, wherein the device comprises a flash memory device.

14. The method of claim 9, wherein the plurality of regions comprises a first region, a second region and a third region.

15. The method of claim 14, wherein forming the trench comprises forming a trench in the second region and the third region.

16. The method of claim 15, wherein the trench in the second region is formed at a first depth and the trench in the third region is formed at a second depth greater than the first depth.

17. The method of claim 14, wherein at least one of the second region and the third region corresponds to a common source wire region of a device.

18. The method of claim 17, wherein the device comprises a flash memory device.

19. An apparatus comprising:

a semiconductor substrate having a plurality of regions including a first region and a second region formed spatially below the first region;

a lower conductive layer formed at the first region over the uppermost surface of the semiconductor substrate and at the at the second region in the semiconductor substrate;

an interlayer insulating layer formed over each lower conductive layer;

a pair of contact plugs formed spaced apart in the interlayer insulating layer and connected electrically to a respective lower conductive layer; and

an upper conductive layer formed over the interlayer insulating layer and electrically connected to a respective lower conductive layer through the contact plugs.

20. The apparatus of claim 19, further comprising a third region formed spatially below the second region, wherein a lower conductive layer is formed at the third region and in the semiconductor substrate.