SEMICONDUCTOR LIGHT EMITTING DEVICE WITH LIGHT EXTRACTION STRUCTURES

• US 20090159908A1
• Filed: 12/19/2007
• Published: 06/25/2009
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J. JR., David, Aurelien J.F., Choy, Henry Kwong-Hin
• Granted Patent: US 7,985,979 B2
• Time in Patent Office: Days
• US Class Current: 257/95
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/26 Materials of the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials

Abstract

Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.

Claims

1. A device comprising:

a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region;

a reflective metal contact disposed on a bottom side of the semiconductor structure and electrically connected to the p-type region;

a material disposed between at least a portion of the reflective metal contact and the p-type region, wherein a difference between an index of refraction of the material and an index of refraction of the p-type region is at least 0.4;

wherein;

at least a portion of a top side of the semiconductor structure is textured; and

a distance between the textured portion of the top side of the semiconductor structure and the reflective metal contact is less than 5 μ

m.

2. The device of claim 1 wherein a difference between an index of refraction of the material and an index of refraction of the p-type region is at least 0.7.

3. The device of claim 1 wherein:

the light emitting layer comprises a III-nitride material; and

the reflective metal contact comprises silver.

4. The device of claim 1 wherein the material is one of a dielectric, an oxide, a semiconductor, SiO₂, SiN, TiO₂, Al₂O₃, ITO, InO, ZnO, CuO, AlInGaN, AlGaN, AlInN, Al_xO_y, Ga_xO_y and Al_xIn_yO_z.

5. The device of claim 1 wherein an interface between the semiconductor structure and the material is configured to reflect light incident on the interface at angles greater than 70°

relative to a normal to a major plane of the light emitting layer.

6. The device of claim 1 wherein a composite reflectivity of the material and the reflective metal contact on the p-type region is greater than a reflectivity of the reflective metal contact in direct contact with the p-type region.

7. The device of claim 1 wherein the material is configured such that a round-trip loss in the material is less than a loss of a visible spectrum wave reflecting off the reflective metal contact in direct contact with the p-type region.

8. The device of claim 1 wherein the textured portion is one of randomly roughened and patterned with a photonic crystal.

9. The device of claim 1 wherein the reflective contact directly contacts the semiconductor structure through openings formed in the material.

10. The device of claim 9 wherein nearest neighbor openings are spaced less than 2 μ

m apart.

11. The device of claim 1 wherein a thickness of the material is less than 500 nm.

12. The device of claim 1 wherein a thickness of the material is greater than 40 nm.

13. The device of claim 1 wherein a thickness of the material is less than half a wavelength of light emitted by the light emitting layer.

14. The device of claim 1 wherein:

a thickness of the material is more than half a wavelength of light emitted by the light emitting layer such that light incident on the material at a range of incident angles is trapped in the material; and

the semiconductor structure is configured to minimize an amount light emitted at the range of incident angles.

15. A device comprising:

a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region; and

a plurality of cavities extending into the semiconductor structure, wherein the cavities are configured to reflect light incident on the interface at angles greater than 70°

relative to a normal to a major plane of the light emitting layer.

16. The device of claim 15 further comprising a reflective metal contact disposed on a bottom side of the semiconductor structure, wherein the plurality of cavities extend from the bottom side of the semiconductor structure toward a top side of the semiconductor structure.

17. The device of claim 15 further comprising a reflective metal contact disposed on a bottom side of the semiconductor structure, wherein the plurality of cavities extend from a top side of the semiconductor structure toward the bottom side of the semiconductor structure.

18. The device of claim 15 wherein the cavities are configured such that a photon traveling within the semiconductor structure cannot travel further than 50 μ

m before interacting with a cavity.

19. The device of claim 15 wherein the cavities have sidewalls oriented at an angle between 35 and 55°

relative to a major surface of the light emitting layer.

20. The device of claim 15 wherein sidewalls of the cavities are coated with a dielectric material.

21. The device of claim 15 wherein nearest neighbor cavities are spaced between 10 and 300 μ

m apart.

22. The device of claim 15 wherein at least one of the cavities is filled with metal that makes electrical contact to the n-type region.

23. The device of claim 15 wherein sidewalls of the cavities are roughened.

24. The device of claim 15 wherein:

at least one of the cavities is filled with metal; and

sidewalls of the cavity filled with metal are coated with a dielectric that electrically isolates the metal from the semiconductor structure.

25. The device of claim 15 wherein the plurality of cavities does not create electrical isolation of any portion of the device.