PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE

• US 20090159971A1
• Filed: 12/19/2007
• Published: 06/25/2009
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Street, Robert A.
• Granted Patent: US 8,110,450 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.

Claims

1. A method of configuring a self-aligning thin film transistor comprising:

forming a gate contact area with a state-switchable material that is initially non-conductive;

forming a gate dielectric which isolates the gate contact area;

forming a source-drain layer, including a source contact and a drain contact with a source-drain layer material;

exposing a portion of the gate contact area to a form of energy, wherein the energy transforms a portion of the state-switchable material which corresponds to the exposed portion of the gate contact area, turning the exposed portion of the state-switchable material from non-conductive to conductive and the exposed portion of the gate contact area to a gate contact; and

forming a semi-conductor layer of a semiconductor material between the source contact and the drain contact.

2. The method according to claim 1 wherein the source-drain layer material is opaque.

3. The method according to claim 1 wherein the dielectric layer is transparent.

4. The method according to claim 1 wherein the energy is at least one of light energy and heat energy.

5. The method according to claim 1 wherein the state-switchable material is one of silver halides, a polymer, an inorganic semiconductor, and a chalcogenide alloy.

6. The method according to claim 1 wherein at least some of the state-switchable material is covered by the drain contact and the source contact, and the drain contact and the source contact block the source of energy from reaching the portion of the state-switchable material located under the drain contact and the source contact.

7. The method according to claim 6 wherein the drain contact and source contact act as a mask to allow only portions of the state-switchable material of the gate contact which does not overlap the drain contact and the source contact to be switched to a conducting state, causing the gate contact, source contact and drain contact to self-align without overlap.

8. The method according to claim 1 wherein parasitic capacitance between the gate and the source or drain is substantially eliminated.

9. The method according to claim 1 wherein at least some of the forming steps include at least one of jet printing, piezoelectric printing, acoustic printing, offset printing, gravure printing or flexographic printing.

10. The method according to claim 1 further including the steps of:

forming a gate address line in operative connection with the gate contact; and

forming a data address line in operative contact with the drain contact.

11. The method according to claim 10 further including forming a plurality of gate contacts, drain contacts, source contacts, gate address lines, data address lines, and semi-conductor layers as an array.

12. The method according to claim 1 wherein the forming and exposing steps form one of a bottom gate TFT or a top gate TFT.

13. A thin film transistor comprising

a gate contact formed from a state-switchable material;

a gate dielectric layer formed over the gate contact;

a source-drain layer including a source contact, and a drain contact formed with a source-drain layer material, wherein any portion of the state-switchable material covered by the source contact and the drain contact is non-conductive and any portion of the state-switchable material not located under the source contact and the drain contact is conductive; and

a semiconductor material formed between the source contact and the drain contact.

14. The thin film transistor according to claim 13 wherein the source-drain layer material is opaque.

15. The thin film transistor according to claim 13 wherein the dielectric layer is transparent.

16. The thin film transistor according to claim 13 wherein the source of energy is at least one of light energy or heat energy.

17. The thin film transistor according to claim 13 wherein at least some of the state-switchable material is covered by the drain contact and the source contact, and the drain contact and the source contact block the source of energy from reaching the portion of the state-switchable material located under the drain contact and the source contact.

18. The thin film transistor according to claim 17 wherein the drain contact and source contact act as a mask to allow only portions of the state-switchable material of the gate contact which does not overlap the drain contact and the source contact to be switched to a conducting state, causing the gate contact, source contact and drain contact to self-align without overlap.

19. The thin film transistor according to claim 13 wherein parasitic capacitance is substantially eliminated.

20. The thin film transistor according to claim 13 further including:

a gate address line in operative connection with the gate contact; and

a data address line in operative contact with the drain contact.

21. The thin film transistor according to claim 20 further including a plurality of gate contacts, drain contacts, source contacts, gate address lines, data address lines, and semi-conductor layers arranged as an array.