METHOD OF FABRICATING MULTI-GATE SEMICONDUCTOR DEVICES WITH IMPROVED CARRIER MOBILITY

• US 20090159972A1
• Filed: 12/19/2008
• Published: 06/25/2009
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Jakschik, Stefan, Collaert, Nadine
• Granted Patent: US 7,842,559 B2
• Time in Patent Office: Days
• US Class Current: 257/350
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

Claims

1. A method of fabricating a multi-gate device comprising:

providing a substrate comprising a first semiconductor layer having at least a first carrier mobility enhancing parameter, a buried insulating layer on the first semiconductor layer, a second semiconductor layer having at least a second carrier mobility enhancing parameter on the buried insulating layer, wherein the first carrier mobility enhancing parameter comprises any of a first crystalline orientation or a first crystalline direction or a first semiconductor material or a first stress or a first combination thereof and wherein the second carrier mobility enhancing parameter comprises any of a second crystalline orientation or a second crystalline direction or a second semiconductor material or a second stress or a second combination thereof, the second carrier mobility enhancing parameter being different from the first carrier mobility enhancing parameter

defining a first active region and a second active region in the substrate, the first active region being electrically isolated from the second active region;

providing a first dielectric layer on the substrate;

providing a second dielectric layer on the first dielectric layer;

forming in the first active region at least a first trench through the first dielectric layer, the second dielectric layer, the second semiconductor layer and the buried insulating layer;

forming a first fin in the at least first trench, the first fin protruding above the first dielectric layer, the first fin having at least the first carrier mobility enhancing parameter;

forming in the second active region at least a second trench through the first dielectric layer and the second dielectric layer;

forming a second fin in the at least second trench, the second fin protruding above the first dielectric layer, the second fin having at least the second mobility enhancing parameter; and

removing the second dielectric layer to expose the first fin and the second fin.

2. The method of fabricating a multi-gate device according to claim 1, wherein the first or second crystalline orientation is chosen from (100), (110), (111).

3. The method of fabricating a multi-gate device according to claim 1, wherein the first or second crystalline direction is chosen from <

100>

, <

110>

, <

111>

.

4. The method of fabricating a multi-gate device according to claim 1, wherein the first active region is electrically isolated from the second active region by electrically isolating a sidewall of the first trench in the first active region from the second semiconductor layer in the second active region.

5. The method of fabricating a multi-gate device according to claim 1, wherein the isolating a sidewall of the first trench comprises depositing a dielectric material at the sidewall.

6. The method of fabricating a multi-gate device, according to claim 1, wherein the second dielectric layer has a thickness (T) such that the first fin protrudes above the first dielectric layer over a first height (H1) equal to or smaller than the thickness (T).

7. The method of fabricating a multi-gate device according to claim 1, wherein the second fin protrudes above the first dielectric layer over a second height (H2) equal to or smaller than the thickness (T).

8. The method of fabricating a multi-gate device according to claim 1, wherein the first height (H1) equals the second height (H2).

9. The method of fabricating a multi-gate device according to claim 1, wherein the forming of the first fin in the at least first trench further comprises filling a bottom part of the first trench by epitaxially growing on the first semiconductor layer a bottom semiconductor material having at least the first carrier mobility enhancing parameter.

10. The method of fabricating a multi-gate device according to claim 9, further comprising filling at least an upper part of the first trench by epitaxially growing on the bottom semiconductor material in the bottom part of the first trench an upper semiconductor material.

11. The method of fabricating a multi-gate device according to claim 1, wherein the f forming of the second fin in the at least second trench further comprises filling a bottom part of the second trench by epitaxially growing on the second semiconductor layer another bottom semiconductor material having at least the second carrier mobility enhancing parameter.

12. The method of fabricating a multi-gate device according to claim 11, further comprising filling an upper part of the second trench by epitaxially growing on the another bottom semiconductor material in the bottom part of the second trench another upper semiconductor material.

13. The method of fabricating a multi-gate device according to claim 10, wherein the filling of at least the bottom part of the second trench is done simultaneously with the filling of the upper part of the first trench.

14. The method of fabricating a multi-gate device according to claim 1, further comprising:

providing a mask on the at least first fin before the forming of the at least second fin; and

removing the mask after the forming of the at least second fin.

15. A multi-gate device comprising:

a substrate comprising;

a first semiconductor layer comprising a first semiconductor material with at least a first carrier mobility enhancing parameter,

a buried insulating layer on the first semiconductor layer, and

a second semiconductor layer comprising a second semiconductor material with at least a second carrier mobility enhancing parameter on the buried insulating layer, the second carrier mobility enhancing parameter being different from the first carrier mobility enhancing parameter;

a first active region and a second active region in the substrate, the first active region being electrically isolated from the second active region, the first active region comprises at least a first fin, the first fin grown on top and in contact with the first semiconductor layer, the first fin comprising at least the first semiconductor material, the second active region comprises at least a second fin, the second fin grown on top and in contact with the second semiconductor layer, the second fin comprising at least the second semiconductor material; and

a dielectric layer over the second semiconductor layer, the dielectric layer in between the at least first fin and the at least second fin, the at least first fin and the at least second fin protruding through and above the dielectric layer.

16. The multi-gate device according to claim 15, wherein the first carrier mobility enhancing parameter is a crystalline orientation or direction of the first semiconductor material and the second carrier mobility enhancing parameter is another crystalline orientation or direction of the second semiconductor material.

17. The multi-gate device according to claim 16, wherein the at least first fin comprises an n-type first semiconductor material having a (100)/<

110>

surface direction/orientation, and wherein the at least second fin comprises a p-type second semiconductor material having a (110)/<

110>

surface direction/orientation.

18. The multi-gate device according to claim 15, the device further comprises:

a gate oxide layer on each fin; and

a gate electrode on the gate oxide layer.

19. The multi-gate device according to claim 18, the device further comprises a source region and a drain region in the active regions at sides of the gate electrode.

20. A method of fabricating a multi-gate device comprising:

providing a first dielectric layer over a substrate and a second dielectric layer over the first dielectric layer, the substrate comprising;

a first semiconductor layer having at least a first carrier mobility enhancing parameter,

an insulating layer over the first semiconductor layer, and

a second semiconductor layer over the insulating layer, the second semiconductor layer having at least a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter;

forming in a first active region of the substrate a first trench through the first dielectric layer, the second dielectric layer, the second semiconductor layer and the buried insulating layer;

forming a first fin in the first trench, the first fin protruding above the first dielectric layer, the first fin having at least the first carrier mobility enhancing parameter;

forming in a second active region a second trench through the first dielectric layer and the second dielectric layer;

forming a second fin in the second trench, the second fin protruding above the first dielectric layer, the second fin having at least the second mobility enhancing parameter; and

removing the second dielectric layer to expose the first fin and the second fin.

21. The method according to claim 20, wherein each of the first and second carrier mobility enhancing parameter comprises any one or more of the following:

a crystalline orientation, a crystalline direction, a semiconductor material, and a stress.

22. The method according to claim 20, wherein the first active region is electrically isolated from the second active region.

23. A multi-gate device as manufactured according to claim 20.