BOOST CONVERTER WITH ADAPTIVE COIL PEAK CURRENT

• US 20090160422A1
• Filed: 12/20/2007
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Inventors: Chiou, Chii-Fa, Isobe, Yuji
• Granted Patent: US 7,906,943 B2
• Time in Patent Office: Days
• US Class Current: 323/349
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/157 with digital control

Abstract

A power conversion circuit operates in a discontinuous switching mode over a wide range of loading conditions and varies a coil peak current to maintain efficiency over the wide range of loading conditions. The coil peak current is adjustable based at least in part on a feedback signal generated in response to a load condition.

Claims

1. A controller for a DC-to-DC power converter, the controller comprising:

a modulator configured to generate a driving signal for alternately turning on and off a switching transistor, wherein the switching transistor conducts a coil current that increases while the switching transistor is on and the driving signal turns off the switching transistor after the coil current reaches a desired peak current level;

a feedback comparator configured to generate a feedback signal based on comparing a target reference with a sensed signal indicative of a load condition; and

a desired peak current circuit configured to generate an output to indicate the desired peak current level and to vary the desired peak current level based at least in part on the feedback signal while the controller operates in a discontinuous switching mode in which the feedback signal transitions to a first state that enables the modulator when the sensed signal is less than the target reference and transitions to a second state that disables the modulator when the sensed signal is greater than the target reference.

2. The controller of claim 1, wherein the desired peak current circuit comprises:

a buffer circuit, wherein an output of the buffer circuit indicates the desired peak current level;

a capacitor coupled to an input of the buffer circuit;

a current source configured to charge the capacitor while the feedback signal is in the first state; and

a current sink configured to discharge the capacitor when the feedback signal transitions from the first state to the second state.

3. The controller of claim 1, wherein the desired peak current circuit varies the desired peak current level in discrete steps.

4. The controller of claim 1, wherein the desired peak current circuit further varies the desired peak current level responsive to a clock signal that tracks the driving signal for the switching transistor.

5. The controller of claim 4, wherein the desired peak current circuit comprises:

a buffer circuit, wherein an output of the buffer circuit indicates the desired peak current level;

a capacitor coupled to an input of the buffer circuit;

a clock divider or a clock counter that receives the clock signal and outputs a one-shot pulse after every M cycles of the clock signal;

a current source configured to charge the capacitor by a first predefined amount in response to the one-shot pulse; and

a current sink configured to discharge the capacitor by a second predefined amount when the feedback signal transitions from the first state to the second state.

6. The controller of claim 4, wherein the desired peak current circuit comprises:

a clock divider or a clock counter that receives the clock signal and outputs a one-shot pulse after every M cycles of the clock signal; and

a binary counter that increases by a first predefined step in response to an up signal and decreases by a second predefined step in response to a down signal, wherein an output of the binary counter indicates the desired peak current level.

7. The controller of claim 6, wherein the down signal decreases the binary counter each time the feedback signal is in the second state for greater than a predetermined duration.

8. The controller of claim 1, wherein the modulator is a pulse frequency modulator comprising:

a peak current comparator configured to compare a detected signal indicative of the coil current with the output from the desired peak current circuit indicative of the desired peak current level;

an off-time generator configured to receive an output of the peak current comparator and to generate a clock signal with substantially fixed inactive durations; and

a driver circuit configured to receive the clock signal and to generate the driving signal for the switching transistor.

9. The controller of claim 1, wherein the modulator comprises:

an oscillator configured to generate a periodic signal with a predetermined frequency, wherein the periodic signal starts active durations of a clock signal at regular intervals;

a peak current comparator configured to compare a detected signal indicative of the coil current with the output from the desired peak current circuit indicative of the desired peak current level, wherein each active duration of the clock signal stops when the coil current exceeds the desired peak current level; and

a driver circuit configured to receive the clock signal and to generate the driving signal for the switching transistor.

10. A method for controlling a switch in a DC-to-DC power converter, the method comprising:

comparing a sensed signal indicative of a load condition with a target reference to generate an outer feedback signal;

varying a desired peak current level responsive to said generated outer feedback signal;

comparing a sensed coil current with the desired peak current level to generate an inner feedback signal;

generating, responsive to said generated inner feedback signal, a driving signal arranged to conducted a temporally increasing coil current through the switch when active and cease conduction through the switch when inactive;

enabling, responsive to a first condition of said outer feedback signal, said driving signal to conduct the current through the switch; and

disabling, substantially over an entire designed load range and responsive to a second condition of said outer feedback signal, said driving signal from conducting the current through the switch.

11. The method of claim 10, wherein the desired peak current level increases linearly responsive to said first condition of said outer feedback signal and decreases to a predetermined level or by a predetermined amount responsive to said second condition of said outer feedback signal.

12. The method of claim 10, wherein the varying of said desired peak current level is in discrete steps.

13. The method of claim 10, wherein the varying of said desired peak current level is suspended during inactive durations in which power is not provided to a load.

14. The method of claim 10, further comprising:

additionally varying the desired peak current level responsive to a clock signal that tracks the driving signal.

15. The method of claim 14, wherein said varying the desired peak current level comprises:

generating a digital word to indicate the desired peak current level; and

increasing the digital word by a predetermined amount when the outer feedback signal does not transition from the first condition to the second condition within M cycles of the clock signal after a previous adjustment to the digital word.

16. The method of claim 15, wherein said varying the desired peak current level further comprises decreasing the digital word by a predetermined amount when the outer feedback signal transitions from the first condition to the second condition.

17. The method of claim 15, wherein said varying the desired peak current level further comprises decreasing the digital word by a predetermined amount when the outer feedback signal transitions from the first condition to the second condition within L cycles of the clock signal.

18. The method of claim 15, wherein said varying the desired peak current level further comprises decreasing the digital word by a predetermined amount when the outer feedback signal is in the second condition for more than a predefined duration.

19. The method of claim 10, wherein the driving signal when enabled sets the switch to conduct the temporally increasing current at periodic intervals for substantially constant frequency operation

20. The method of claim 10, wherein the driving signal when enabled has substantially fixed inactive durations for pulse frequency modulation operation.

21. A controller comprising:

a means for generating a feedback signal that indicates whether a load condition is above a reference level or below the reference level;

a means for generating a driving signal to alternately turn on and off a semiconductor switch, wherein the semiconductor switch turns on for a duration that varies with a desired peak current level; and

a means for adjusting the desired peak current level based on the feedback signal while the controller operates in a discontinuous switching mode in which the driving signal is enabled and disabled responsive to different conditions of said feedback signal.

22. The controller of claim 21, wherein the desired peak current level is adjustable in discrete steps.

23. The controller of claim 21, wherein the desired peak current level is further adjustable based on the driving signal.

24. The controller of claim 23, further comprising a means for counting a number of switching cycles in the driving signal and increasing the desired peak current level when the number of switching cycles exceeds a predetermined amount since a previous adjustment to the desired peak current level.

25. The controller of claim 21, wherein the desired peak current level decreases when the feedback signal changes from a first condition to a second condition.

26. The controller of claim 21, wherein the desired peak current level increases when the feedback signal condition indicates that the load condition is below the reference level.