Formation of a hybrid integrated circuit device

• US 20090160482A1
• Filed: 12/20/2007
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J., Young, Steven P., Karp, James, Nance, Scott S., Crotty, Patrick J.
• Granted Patent: US 7,919,845 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/37001 : Yield
• CPC Class Codes: H03K 19/177 : arranged in matrix form

Abstract

Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).

Claims

1. A method for forming a hybrid integrated circuit device, comprising

obtaining a design for an integrated circuit;

separating the design into at least two portions, the at least two portions separated out responsive to component sizes;

associating a first portion of the at least two portions for being formed using greater than or equal to a first minimum dimension lithography;

associating a second portion of the at least two portions for being formed using greater than or equal to a second minimum dimension lithography, the second minimum dimension lithography being greater in size than the first minimum dimension lithography;

forming a first die for the first portion using at least in part the first minimum dimension lithography, the first die having the first minimum dimension lithography as a smallest lithography used for the forming of the first die;

forming a second die for the second portion using at least in part the second minimum dimension lithography, the second die having the second minimum dimension lithography as a smallest lithography used for the forming of the second die; and

attaching the first die and the second die to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.

2. The method according to claim 1, wherein attaching the first die and the second die comprises coupling the first portion to interface logic of the second die and coupling the second portion to interface logic of the first die;

and the method further comprising;

attaching the second die to an interconnect substrate.

3. The method according to claim 1, wherein the first die includes at least one circuit selected from the group consisting of random access memory, programmable logic, an embedded processor, and digital signal processing blocks;

and

wherein the second die includes at least one circuit selected from the group consisting of multi-gigabit transceivers, input/output blocks, and a network interface.

4. The method according to claim 3, wherein the second die further includes at least one circuit selected from the group consisting of configuration ports, a system monitor, clock management tiles, and non-volatile memory.

5. The method according to claim 1, wherein the first minimum dimension lithography is approximately 25 to 75 percent smaller than the second minimum dimension lithography.

6. The method according to claim 1, wherein the first minimum dimension lithography is an x-ray lithography;

and wherein the second minimum dimension lithography is a photolithography.

7. The method according to claim 1, wherein the first minimum dimension lithography is a direct write lithography;

and

wherein the second minimum dimension lithography is a photolithography.

8. The method according to claim 1, wherein the first minimum dimension lithography is a direct write lithography;

and

wherein the second minimum dimension lithography is an x-ray lithography.

9. The method according to claim 1 further comprising upgrading one of the first die and the second die without having to change the other one of the first die and the second die.

10. A method for formation of a hybrid integrated circuit device, comprising:

associating components of an integrated circuit design into cost categories, the cost categories broken out at least in part according to minimum lithographic dimensions used for forming the components;

parsing the integrated circuit into at least two component groups, a first group of the at least two component groups being associated with higher manufacturing cost due to use of smaller lithographic features than a second group of the at least two component groups;

forming a first die for the first group using greater than or equal to a first minimum dimension lithography and a second die for the second group using greater than or equal to a second minimum dimension lithography, the first minimum dimension lithography having smaller feature sizes than the second minimum dimension lithography;

the first die having the first minimum dimension lithography as a smallest lithography used for the forming of the first group;

the second die having the second minimum dimension lithography as a smallest lithography used for the forming of the second group; and

the first die and the second die each formed to include circuitry for coupling the first die and the second die to one another for providing the hybrid integrated circuit device.

11. The method according to claim 10, wherein the first minimum dimension lithography is approximately 25 to 75 percent smaller than the second minimum dimension lithography.

12. The method according to claim 10, wherein the first minimum dimension lithography is an x-ray lithography;

and

wherein the second minimum dimension lithography is a photolithography.

13. The method according to claim 10, wherein the first minimum dimension lithography is a direct write-lithography;

and

wherein the second minimum dimension lithography is a photolithography.

14. The method according to claim 10, wherein the first minimum dimension lithography is a direct write lithography;

and

wherein the second minimum dimension lithography is an x-ray lithography.

15. A hybrid integrated circuit device, comprising:

a first die;

a second die having pins for input and output connectivity;

the first die having circuitry for storing information obtained via the pins and for outputting information via the pins;

the first die and the second die representing separate portions of an integrated circuit product;

the first die and the second die coupled to one another, wherein the first die and the second die each include interconnects for coupling the first die and the second die to one another for electrical communication therebetween;

the first die associated with a first lithography for formation of a first feature size;

the second die associated with a second lithography for formation of a second feature size;

the second feature size of the second die being larger than the first feature size of the first die; and

the second die having no circuitry with the first feature size.

16. The hybrid integrated circuit device according to claim 15, wherein the first die comprises programmable logic and internal random access memory;

and

wherein the second die is comprises input/output circuitry.

17. The hybrid integrated circuit device according to claim 15, wherein the first die is separately manufacturable from the second die.

18. The hybrid integrated circuit device according to claim 15, wherein the first die and the second die are coupled to one another via microbonding;

and

wherein the first die includes a flip-chip interface for coupling to an interconnect substrate.

19. The hybrid integrated circuit device according to claim 15, wherein the first die and the second die are coupled to one another via microbonding;

and

wherein a portion of an upper surface area of the first die is exposed for wirebonding thereto even after the first die and the second die are coupled to one another.

20. The hybrid integrated circuit device according to claim 19, wherein the first die and the second die in combination provide a programmable logic device.