Phase and frequency detector with zero static phase error

• US 20090160487A1
• Filed: 12/19/2007
• Published: 06/25/2009
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Hu, Pengfei, Qiao, Juan, Chang, Zhongyuan
• Granted Patent: US 7,598,775 B2
• Time in Patent Office: Days
• US Class Current: 327/3
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

Claims

1. A phase and frequency detector comprising:

a first phase and frequency detector configured to generate first and second pulsed signals in response to a comparison between a defined occurrence of first and second input signals, the first phase and frequency detector including first and second D-type flip-flops,

wherein the clocking terminals of the first and second D-type flip-flops are configured to receive the first and second input signals respectively, the D terminals of the first and second D-type flip-flops are set to an asserted state, and the Q outputs of the first and second D-type flip-flops provide the first and second pulsed signals respectively;

a reset signal generator configured to provide a reset signal to the reset terminals of the first and second D-type flip-flops based on the state of the first and second pulsed signals,

wherein the reset signal generator includes an AND gate enabled by the first and second pulse signals and a delay buffer configured to delay the output the AND gate by a set delay to provide the reset signal; and

a pulse blocker that receives the first and second pulsed signals and provides first and second output signals,

wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted.

2. The phase and frequency detector of claim 1, wherein the defined occurrence is the occurrence of a rising signal edge.

3. The phase and frequency detector of claim 1, wherein the defined occurrence is the occurrence of a falling signal edge.

6. The phase and frequency detector circuit of claim 1, wherein the pulse blocker comprises:

first and second NAND gates, wherein the first NAND gate is enabled by the first pulsed signal and the output of the second NAND gate, and the second NAND gate is enabled by the second pulsed signal and the output of the first NAND gate;

a first inverter configured to invert the output of the first NAND gate and provide the first output signal; and

a second inverter configured to invert the output of the second NAND gate and provide the second output signal.

4-5. -5. (canceled)

7. A method for detecting the phase difference between a first and a second input signal, the method comprising:

providing a first input signal to a first clocking terminal of a first D-type flip-flop;

providing a second input signal to a second clocking terminal of a second D-type flip-flop;

providing a high logic level signal to a first D input of the first D-type flip-flop and a second D input of the second-D-type flip flop;

generating, at a first output of the first D-type flip-flop, a first pulsed signal in response to a first defined occurrence of the first input signal;

generating, at a second output of the first D-type flip-flop, a second pulsed signal in response to a second defined occurrence of the second input signal;

generating, by a reset signal generator, a reset signal at a fixed delay from an occurrence of the first and second pulsed signals both being asserted;

providing the reset signal to a first reset terminal of the first D-type flip-flop and the second reset terminal of the second D-type flip flop; and

generating first and second output signals based on the first and second pulsed signals respectively,

wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted.

8. The method of claim 7, wherein the first and second defined occurrences the occurrence of a rising signal edge.

9. The method of claim 7, wherein the first and second defined occurrences are the occurrence of a falling signal edge.