SEMICONDUCTOR INTEGRATED CIRCUIT
First Claim
1. A semiconductor integrated circuit comprising a phase-locked loop circuit including:
- a phase-frequency comparator;
a first charge pump;
a second charge pump;
a loop filter;
a voltage-control oscillator;
a voltage-control oscillator; and
a divider,wherein the phase-frequency comparator compares a reference signal with a feedback signal made by an output signal of the divider in phase difference, and produces first and second output signals as phase comparison output signals resulting from the comparison,wherein the first and second charge pumps are made operable to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator respectively,wherein outputs of the first and second charge pumps are connected to the loop filter,wherein an operation mode of the PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued,wherein, in the steady lock operation of the PLL circuit in which a phase of the reference signal and a phase of the feedback signal from the divider are kept in a state of being locked in a predetermined relation, setting is made so that charge/discharge current of the output of the second charge pump is smaller than charge/discharge current of the output of the first charge pump in current value,wherein, in the operation mode of the steady lock operation of the PLL circuit, the first and second charge pumps respond to the first and second output signals of the phase-frequency comparator to charge and discharge the loop filter in reverse to each other in phase, andwherein, in the lock response operation in which the locking is started, the second charge pump is stopped from charging and discharging the loop filter in reverse in phase to the charging and discharging of the loop filter by the first charge pump.
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Accused Products
Abstract
The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.
22 Citations
14 Claims
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1. A semiconductor integrated circuit comprising a phase-locked loop circuit including:
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a phase-frequency comparator; a first charge pump; a second charge pump; a loop filter; a voltage-control oscillator; a voltage-control oscillator; and a divider, wherein the phase-frequency comparator compares a reference signal with a feedback signal made by an output signal of the divider in phase difference, and produces first and second output signals as phase comparison output signals resulting from the comparison, wherein the first and second charge pumps are made operable to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator respectively, wherein outputs of the first and second charge pumps are connected to the loop filter, wherein an operation mode of the PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued, wherein, in the steady lock operation of the PLL circuit in which a phase of the reference signal and a phase of the feedback signal from the divider are kept in a state of being locked in a predetermined relation, setting is made so that charge/discharge current of the output of the second charge pump is smaller than charge/discharge current of the output of the first charge pump in current value, wherein, in the operation mode of the steady lock operation of the PLL circuit, the first and second charge pumps respond to the first and second output signals of the phase-frequency comparator to charge and discharge the loop filter in reverse to each other in phase, and wherein, in the lock response operation in which the locking is started, the second charge pump is stopped from charging and discharging the loop filter in reverse in phase to the charging and discharging of the loop filter by the first charge pump. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor integrated circuit for interface connectable between a storage disk device and a host device, comprising:
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a record-and-reproduction unit arranged to be connectable with the storage disk device and including a first PLL circuit; and an interface unit arranged to be connectable with the host device and including second PLL circuits, wherein the semiconductor integrated circuit reads a read signal from the storage disk device to supply read data to the host device, and accepts write data from the host device to supply a write signal to the storage disk device, wherein the record-and-reproduction unit of the semiconductor integrated circuit reads the read signal from the storage disk device to supply the write signal to the storage disk device, wherein the interface unit of the semiconductor integrated circuit accepts the write data from the host device to supply the write signal to the storage disk device, wherein the first PLL circuit and second PLL circuits each include a phase-frequency comparator, first and second charge pumps, a loop filter, a voltage-control oscillator and a divider, wherein the phase-frequency comparator of each PLL circuit compares a reference signal with a feedback signal made by an output signal of the divider in phase difference, and outputs first and second output signals as phase comparison output signals resulting from the comparison, wherein the first and second charge pumps of each PLL circuit are made operable to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator respectively, wherein outputs of the first and second charge pumps of each PLL circuit are connected to the loop filter, wherein an operation mode of each PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued, wherein, in the steady lock operation of each PLL circuit, in which a phase of the reference signal and a phase of the feedback signal from the divider are kept in a state of being locked in a predetermined relation, setting is made so that charge/discharge current of the output of the second charge pump is smaller than charge/discharge current of the output of the first charge pump in current value, wherein, in the operation mode of the steady lock operation of each PLL circuit, the first and second charge pumps respond to the first and second output signals of the phase-frequency comparator to charge and discharge the loop filter in reverse to each other in phase, wherein, in the lock response operation of each PLL circuit in which locking is started, the second charge pump is stopped from charging and discharging the loop filter in reverse in phase to the charging and discharging of the loop filter by the first charge pump, wherein the second PLL circuits each include a modulator connected with the divider thereof, and wherein the divider of the second PLL circuit varies in division factor between difference values responding to an output of the modulator, and thus the second PLL circuit operates, as a fractional PLL that an average division factor of the divider is constituted by a sum of an integer part and a decimal part, in a fractional PLL operation mode. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification