SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20090160565A1
• Filed: 12/17/2008
• Published: 06/25/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kawamoto, Takashi
• Granted Patent: US 7,859,345 B2
• Time in Patent Office: Days
• US Class Current: 331/1.A
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Claims

1. A semiconductor integrated circuit comprising a phase-locked loop circuit including:

a phase-frequency comparator;

a first charge pump;

a second charge pump;

a loop filter;

a voltage-control oscillator;

a voltage-control oscillator; and

a divider,

wherein the phase-frequency comparator compares a reference signal with a feedback signal made by an output signal of the divider in phase difference, and produces first and second output signals as phase comparison output signals resulting from the comparison,

wherein the first and second charge pumps are made operable to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator respectively,

wherein outputs of the first and second charge pumps are connected to the loop filter,

wherein an operation mode of the PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued,

wherein, in the steady lock operation of the PLL circuit in which a phase of the reference signal and a phase of the feedback signal from the divider are kept in a state of being locked in a predetermined relation, setting is made so that charge/discharge current of the output of the second charge pump is smaller than charge/discharge current of the output of the first charge pump in current value,

wherein, in the operation mode of the steady lock operation of the PLL circuit, the first and second charge pumps respond to the first and second output signals of the phase-frequency comparator to charge and discharge the loop filter in reverse to each other in phase, and

wherein, in the lock response operation in which the locking is started, the second charge pump is stopped from charging and discharging the loop filter in reverse in phase to the charging and discharging of the loop filter by the first charge pump.

2. The semiconductor integrated circuit according to claim 1,

wherein, in the standby state of the operation mode of the PLL circuit, at least the phase-frequency comparator, first and second charge pumps, and divider of the PLL circuit are controlled to be in cutoff states,

wherein a control signal for changing the operation mode of the PLL circuit from the standby state to the lock response operation is supplied to the PLL circuit,

wherein at least the phase-frequency comparator, first charge pump and divider of the PLL circuit are released from the cutoff states and start operating in response to supply of the control signal to the PLL circuit,

wherein the PLL circuit further includes a controller which produces a control output signal changing in level behind by a predetermined delay time in response to a change in level of the control signal, and

wherein, in response to change in level of the control output signal produced by the controller, stop of the second charge pump charging and discharging in reverse in phase in the lock response operation is terminated, and the charging and discharging by the second charge pump in reverse in phase is started in the steady lock operation.

3. The semiconductor integrated circuit according to claim 2,

wherein the PLL circuit further includes a modulator connected to the divider, and

wherein the divider varies in division factor between difference values responding to an output of the modulator, and thus the PLL circuit operates, as a fractional PLL that an average division factor of the divider is constituted by a sum of an integer part and a decimal part, in a fractional PLL operation mode.

4. The semiconductor integrated circuit according to claim 3, further comprising:

an on-chip serial ATA interface unit,

wherein the PLL circuit which operates in the fractional PLL operation mode constitutes a spread spectrum clock generator used in the on-chip serial ATA interface unit.

5. The semiconductor integrated circuit according to claim 4,

wherein the semiconductor integrated circuit including the serial ATA interface unit can be connected between a storage disk device and a host device, and

wherein the semiconductor integrated circuit reads a read signal from the storage disk device to supply the read data to the host device, and accepts write data from the host device to supply a write signal to the storage disk device.

6. The semiconductor integrated circuit according to claim 5,

wherein the first and second output signals of the phase-frequency comparator can be supplied to charge and discharge control input terminals of the first charge pump respectively, and

wherein the second and first output signals of the phase-frequency comparator can be supplied to charge and discharge control input terminals of the second charge pump, respectively.

7. The semiconductor integrated circuit according to claim 6,

wherein outputs of the first and second charge pumps are respectively connected to one end of a resistance of the loop filter and the other end of the resistance, and

wherein a capacitance is connected between the other end of the resistance and a ground potential.

8. The semiconductor integrated circuit according to claim 2,

wherein in the lock response operation in which the lock operation is started, the first and second charge pumps charge and discharge the loop filter in phase with each other.

9. A semiconductor integrated circuit for interface connectable between a storage disk device and a host device, comprising:

a record-and-reproduction unit arranged to be connectable with the storage disk device and including a first PLL circuit; and

an interface unit arranged to be connectable with the host device and including second PLL circuits,

wherein the semiconductor integrated circuit reads a read signal from the storage disk device to supply read data to the host device, and accepts write data from the host device to supply a write signal to the storage disk device,

wherein the record-and-reproduction unit of the semiconductor integrated circuit reads the read signal from the storage disk device to supply the write signal to the storage disk device,

wherein the interface unit of the semiconductor integrated circuit accepts the write data from the host device to supply the write signal to the storage disk device,

wherein the first PLL circuit and second PLL circuits each include a phase-frequency comparator, first and second charge pumps, a loop filter, a voltage-control oscillator and a divider,

wherein the phase-frequency comparator of each PLL circuit compares a reference signal with a feedback signal made by an output signal of the divider in phase difference, and outputs first and second output signals as phase comparison output signals resulting from the comparison,

wherein the first and second charge pumps of each PLL circuit are made operable to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator respectively,

wherein outputs of the first and second charge pumps of each PLL circuit are connected to the loop filter,

wherein an operation mode of each PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued,

wherein, in the steady lock operation of each PLL circuit, in which a phase of the reference signal and a phase of the feedback signal from the divider are kept in a state of being locked in a predetermined relation, setting is made so that charge/discharge current of the output of the second charge pump is smaller than charge/discharge current of the output of the first charge pump in current value,

wherein, in the operation mode of the steady lock operation of each PLL circuit, the first and second charge pumps respond to the first and second output signals of the phase-frequency comparator to charge and discharge the loop filter in reverse to each other in phase,

wherein, in the lock response operation of each PLL circuit in which locking is started, the second charge pump is stopped from charging and discharging the loop filter in reverse in phase to the charging and discharging of the loop filter by the first charge pump,

wherein the second PLL circuits each include a modulator connected with the divider thereof, and

wherein the divider of the second PLL circuit varies in division factor between difference values responding to an output of the modulator, and thus the second PLL circuit operates, as a fractional PLL that an average division factor of the divider is constituted by a sum of an integer part and a decimal part, in a fractional PLL operation mode.

10. The semiconductor integrated circuit according to claim 9,

wherein, in the standby state of the operation mode of each PLL circuit, at least the phase-frequency comparator, first and second charge pumps and divider of the PLL circuit are controlled to be in cutoff states,

wherein a control signal for changing the operation mode of each PLL circuit from the standby state to the lock response operation is supplied to the PLL circuit.

Wherein at least the phase-frequency comparator, first charge pump and divider of each PLL circuit are released from the cutoff states and start operating in response to supply of the control signal to the PLL circuit,

Wherein each PLL circuit further includes a controller which produces a control output signal changing in level behind by a predetermined delay time in response to a change in level of the control signal, and

Wherein, in each PLL circuit, in response to a change in level of the control output signal produced by the controller, stop of the second charge pump charging and discharging in reverse in phase in the lock response operation is terminated, and the charging and discharging by the second charge pump in reverse in phase is started in the steady lock operation.

11. The semiconductor integrated circuit according to claim 10,

wherein the first and second output signals of the phase-frequency comparator can be supplied to charge and discharge control input terminals of the first charge pump of each PLL circuit, respectively, and

wherein the second and first output signals of the phase-frequency comparator can be supplied to charge and discharge control input terminals of the second charge pump of each PLL circuit respectively.

12. The semiconductor integrated circuit according to claim 11,

wherein outputs of the first and second charge pumps of each PLL circuit are respectively connected to one end of a resistance of the loop filter, and the other end of the resistance, and

wherein a capacitance is connected between the other end of the resistance and a ground potential.

13. The semiconductor integrated circuit according to claim 10, further comprising:

a spread spectrum clock generator used in the interface unit arranged as a serial ATA interface unit,

wherein the spread spectrum clock generator includes the second PLL circuits.

14. The semiconductor integrated circuit according to claim 10,

wherein in the lock response operation in which locking is started, the first and second charge pumps charge and discharge the loop filter in phase with each other.