Compact Power Semiconductor Package and Method with Stacked Inductor and Integrated Circuit Die

• US 20090160595A1
• Filed: 02/23/2009
• Published: 06/25/2009
• Est. Priority Date: 11/23/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Zhang, Xiaolian, Sun, Ming, Feng, Tao, Hebert, Francois
• Granted Patent: US 7,868,431 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2027/2814 with only part of the coil or of the winding in the printed circuit board, e.g. the remaining coil or winding sections can be made of wires or sheets
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

Claims

1. A compact power semiconductor package comprising:

a bonded stack of a bottom power Integrated Circuit (IC) die, a top power inductor and an intervening circuit substrate;

said power inductor further comprises a inductor core with an interior window, in the form of a closed magnetic loop, located atop the circuit substrate;

said circuit substrate further comprises a bottom half-coil forming means constituting a bottom half-coil beneath the inductor core; and

a top half-coil forming means located atop the inductor core and interconnected with the bottom half-coil forming means so as to jointly form an inductive coil enclosing the inductor core

whereby realizing a compact power semiconductor package with high inductance rating while exhibiting a reduced package foot print.

2. The power semiconductor package of claim 1 wherein ones of the top half-coil forming means couple the ends of ones of the bottom half-coil forming means exposed through the interior window of the inductor core to the ends of adjacent ones of the bottom half-coil forming means outside the inductor core to form the inductive coil.

3. The power semiconductor package of claim 1 wherein the power IC die is configured with its substrate side structured to bond to a bottom surface of the circuit substrate and the device side of the power IC die facing away from the circuit substrate.

4. The power semiconductor package of claim 3 wherein the device side of said power IC die further comprises a plurality of bottom contact bumps formed thereon for making external connections from the power IC die.

5. The power semiconductor package of claim 1 further comprises a top encapsulant protectively encasing the inductor core, the top half-coil forming means, the bottom half-coil forming means and the circuit substrate.

6. The power semiconductor package of claim 5 wherein the top encapsulant further comprises a molding compound with embedded magnetic particles to increase the inductance rating.

7. The power semiconductor package of claim 1 wherein:

said circuit substrate further comprises a leadframe and said bottom half-coil forming means further comprises a plurality of half-coil patterned conductive leads that are part of the leadframe; and

said leadframe further comprises a bottom recess sized to accommodate the power IC die.

8. The power semiconductor package of claim 1 wherein said circuit substrate further comprises:

a top leadframe and said bottom half-coil forming means further comprises a plurality of half-coil patterned conductive leads that are part of the top leadframe; and

a bottom leadframe matching the top leadframe with an interior hole of pre-determined geometry patterned therein and said bottom leadframe being further laminated to the bottom of the top leadframe so as to form a bottom recess sized to accommodate the power IC die.

9. The power semiconductor package of claim 1 wherein said top half-coil forming means further comprises a plurality of bond wires each looping the inductor core from above and further connecting with proper alternative members of the bottom half-coil forming means whereby forming the inductive coil.

10. The power semiconductor package of claim 1 wherein said top half-coil forming means further comprises a plurality of three dimensionally formed interconnection plates each connecting with proper alternative members of the bottom half-coil forming means whereby forming the inductive coil.

11. The power semiconductor package of claim 1 wherein said top half-coil forming means further comprises a plurality of upper leadframe leads, each connecting with proper alternative members of the bottom half-coil forming means whereby forming the inductive coil.

12. The power semiconductor package of claim 1 wherein said circuit substrate comprises a multi-layer circuit laminate (MCL) further comprising:

a top conductive trace layer having a plurality of half-coil patterned conductive traces constituting the bottom half-coil forming means and a plurality of top conductive traces;

a bottom conductive trace layer having a plurality of bottom conductive traces; and

an intervening insulation layer for isolating the top conductive trace layer from the bottom conductive trace layer.

13. The power semiconductor package of claim 12 wherein:

said intervening insulation layer further comprises a plurality of conductive through holes for electrically connecting a first number of selected half-coil patterned conductive traces with a second number of selected bottom conductive traces whereby making electrical connection between the power IC die and the power inductor.

14. The power semiconductor package of claim 12 wherein the power IC die is configured with its device side structured to bond to a bottom surface of the MCL and the substrate side of the power IC die facing away from the MCL, wherein contacts on the device side of the power IC die are routed out to the periphery of the MCL.

15. The power semiconductor package of claim 12 wherein said MCL further comprises a bottom recess sized to accommodate the power IC die.

16. The power semiconductor package of claim 12 wherein said MCL is a printed circuit board.

17. The power semiconductor package of claim 12 wherein said MCL is a bismaleimide-triazine (BT) substrate.

18. The power semiconductor package of claim 12 wherein said MCL has three conductive trace layers, separated by two insulating layers.

19. The power semiconductor package of claim 1 wherein:

the power inductor has an inductance ranging from about 0.2 micro Henry to about 10 micro Henry with a current rating ranging from about 0.2 Ampere to about 5 Ampere; and

the corresponding package foot print is less than about 5 mm×

5 mm with package thickness less than about 2 mm.

20. The power semiconductor package of claim 1 further comprising:

a plurality of peripheral standoff bumps on the bottom surface of the circuit substrate with the peripheral standoff bumps further sized to accommodate the power IC die.

21. A multi-package process for making multiple compact power semiconductor package units each comprising:

a stack of bottom power IC die, top power inductor and an intervening circuit substrate;

the power inductor comprises a inductor core, with an interior window, of closed magnetic loop located atop the circuit substrate;

the circuit substrate comprises a bottom half-coil forming means beneath the inductor core; and

a top half-coil forming means interconnected with the bottom half-coil forming means jointly forming an inductive coil enclosing the inductor core;

the method comprises;

a) providing a set of multiple circuit substrates with each circuit substrate having the bottom half-coil forming means thereon;

b) providing then structuring multiple power IC dies so that each power IC die is ready for a chip bonding process;

c) providing multiple inductor cores with interior windows and multiple top half-coil forming means;

d) attaching a inductor core to each bottom half-coil forming means;

e) at each circuit substrate location along the set,

e1) aligning a top half-coil forming means atop the inductor core and interconnecting the top half-coil forming means with the bottom half-coil forming means to form a sub-package unit with an inductive coil about the inductor core;

e2) applying a top encapsulant protectively encasing the top of each sub-package unit; and

e3) aligning and bonding a power IC die beneath the sub-package unit to form a package unit; and

f) separating the package unit from the set.

22. The multi-package process of claim 21 wherein ones of the top half-coil forming means couple the ends of ones of the bottom half-coil forming means exposed through the interior window of the inductor core to the ends of adjacent ones of the bottom half-coil forming means outside the inductor core to form the inductive coil.

23. The multi-package process of claim 21 wherein each circuit substrate is made of a leadframe with the bottom half-coil forming means further including a plurality of half-coil patterned conductive leads being part of the leadframe and:

step a) further comprises, as part of the leadframe, adding an interim joining area connecting the half-coil patterned conductive leads together to facilitate subsequent handling of each sub-package unit; and

step e2) further comprises;

e21) insuring that the top encapsulant is electrically non-conductive and bonds together the half-coil patterned conductive leads;

then

e22) removing the interim joining area from the leadframe so as to clear an otherwise short-circuit condition amongst the half-coil patterned conductive leads.

24. The multi-package process of claim 21 wherein patterning the set of multiple circuit substrates further comprises creating, on each circuit substrate, a bottom recess sized to accommodate the power IC die.

25. The multi-package process of claim 24 wherein creating a bottom recess further comprises etching the bottom side of said each circuit substrate.

26. The multi-package process of claim 24 wherein creating a bottom recess further comprises partially sawing the bottom side of said each circuit substrate.

27. The multi-package process of claim 24 wherein the circuit substrate is made of leadframe and creating a bottom recess further comprises:

providing a top leadframe with a plurality of half-coil patterned conductive traces forming the bottom half-coil forming means; and

providing a bottom leadframe with an interior hole of pre-determined geometry patterned therein and further laminating the bottom leadframe to the bottom of the top leadframe so as to form the bottom recess.

28. The multi-package process of claim 21 further comprises attaching a plurality of peripheral bumps onto the bottom of each circuit substrate.