Autonomous Context Scheduler For Graphics Processing Units

• US 20090160867A1
• Filed: 12/19/2007
• Published: 06/25/2009
• Est. Priority Date: 12/19/2007
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Grossman, Mark S.
• Application Number:
  US11/960,305
• Publication Number:
  US 20090160867A1
• Time in Patent Office: Days
• US Class Current: 345/522
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

Embodiments directed to an autonomous graphics processing unit (GPU) scheduler for a graphics processing system are described. Embodiments include an execution structure for a host CPU and GPU in a computing system that allows the GPU to execute command threads in multiple contexts in a dynamic rather than fixed order based on decisions made by the GPU. This eliminates a significant amount of CPU processing overhead required to schedule GPU command execution order, and allows the GPU to execute commands in an order that is optimized for particular operating conditions. The context list includes parameters that specify task priority and resource requirements for each context. The GPU includes a scheduler component that determines the availability of system resources and directs execution of commands to the appropriate system resources, and in accordance with the priority defined by the context list.

Claims

1. An apparatus comprising:

one or more processing engines configured to execute at least a portion of executable program instructions, said executable program instructions belonging to at least one context of a context list, the context list comprising a plurality of contexts, each context containing working data, pointers and scheduling information for the executable program instructions, and a priority level and resource requirements for the context; and

a scheduler coupled to the one or more processing engines and causing processing of contexts in the context list in an order determined by the priority level and resource requirements of the contexts.

2. The apparatus of claim 1 wherein the one or more processing engines comprise components of a graphics processing unit for coupling to the host CPU over an interface bus.

3. The apparatus of claim 2 wherein the resource requirements are selected from the group consisting of:

memory requirements, available processing engines, and power consumption requirements.

4. The apparatus of claim 3 wherein each context further contains a context identifier, and one or more pointers to memory locations for read/write operations of the one or more processing engines.

5. The apparatus of claim 4 wherein each context further contains a time slice size parameter specifying a maximum amount of time allotted to execute program instructions for each context scheduled.

6. The apparatus of claim 1 wherein the scheduler includes a dispatcher module configured to switch execution from a first context to a second context in the event of context switch trigger.

7. The apparatus of claim 6 wherein the context switch trigger is selected from the group consisting of:

a hardware fault condition, a software fault condition, a process exception condition, completion of execution of executable program instructions for the first context, and passage of a maximum amount of time available for completion of the executable program instructions for the first context, and wherein the maximum amount of time may be specified within the context or by a global system parameter.

8. The apparatus of claim 7 wherein the scheduler includes a reporting module configured to provide a report to a host CPU in the event of a context switch.

9. The apparatus of claim 8 wherein the report includes information items selected from the group consisting of:

time spent in the first context, resources used for the first context, memory moved for the first context, and resources not available for the first context.

10. The apparatus of claim 6 wherein the scheduler defines the context processing schedule based on a prioritization scheme that weighs each of the priority level and resource requirements of each context relative to the priority level and resource requirements of the plurality of contexts.

11. The apparatus of claim 10 wherein the prioritization scheme assigns precedence of context execution to contexts with higher priority levels.

12. The apparatus of claim 10 wherein the prioritization scheme assigns precedence of context execution to contexts with lower resource requirements.

13. A method for scheduling command thread execution in a graphics processing unit (GPU), comprising:

defining a plurality of contexts containing working data, pointers and scheduling information for one or more command threads executed by the GPU;

specifying a relative priority for processing of each context of the plurality of contexts, within each respective context; and

determining an order of processing of each context of the plurality of contexts within a scheduling component of the GPU based on the relative priority of each context.

14. The method of claim 13 further comprising:

specifying resource requirements for the processing of each context of the plurality of contexts, within each respective context; and

wherein determining an order of processing of each context of the plurality of contexts within the scheduling component of the GPU is based on the relative priority and resource requirements of each context.

15. The method of claim 14 wherein the resource requirements are selected from the group consisting of:

memory requirements, available processing engines, and power consumption requirements.

16. The method of claim 15 wherein the step of determining the order of processing further comprises determining an amount of time required to complete execution of the context.

17. The method of claim 16 wherein the scheduling component switches processing from a first context to a second context in the event of context switch trigger.

18. The method of claim 17 wherein the context switch trigger is selected from the group consisting of:

a hardware fault condition, a software fault condition, a process exception condition, completion of execution of executable program instructions for the first context, and passage of a defined maximum amount of time available for completion of the executable program instructions for the first context.

19. The method of claim 18 wherein the scheduling component provides a report to a host central processing unit (CPU) in the event of a context switch.

20. The method of claim 19 wherein the report includes information items selected from the group consisting of:

time spent processing the first context, resources used for the first context, memory moved for the first context, and resources not available for the first context.

21. A graphics processor control circuit comprising:

a bus interface circuit coupling a memory to one or more graphics processing engines contained in a graphics processing unit (GPU), wherein the memory stores a context list including a plurality of contexts, each context containing working data, pointers and scheduling information for executable program instructions, and a priority level for the context and resource requirements for the context;

a scheduler in the GPU determining an order of execution of contexts in the context list based on the priority level and resource requirements of the contexts.

22. The graphics processor control circuit of claim 21 wherein the bus interface circuit couples the GPU to a host central processing unit (CPU) in a graphics processing subsystem of a computing device, and wherein the computing device is selected from the group consisting of:

a personal computer, a workstation, a handheld computing device, a digital television, a media playback device, and a game console.

23. The graphics processor control circuit of claim 22 wherein the resource requirements are selected from the group consisting of:

memory requirements, available processing engines of the one or more graphics processing engines, and power consumption requirements.

24. The graphics processor control circuit of claim 23 wherein each context further contains a time slice size parameter specifying a maximum amount of time allotted to execute program instructions for each context scheduled.

25. The graphics processor control circuit of claim 24 wherein the scheduler includes a dispatcher module configured to switch execution from a first context to a second context in the event of context switch trigger, and wherein the context switch trigger is selected from the group consisting of:

a hardware fault condition, a software fault condition, a process exception condition, completion of execution of executable program instructions for the first context, and passage of a maximum amount of time available for completion of the executable program instructions for the first context.

26. A method of operating a computer system comprising:

defining a plurality of contexts containing command threads for execution by a graphics processing unit (GPU); and

determining an order of execution of each context of the plurality of contexts within a scheduling component of the GPU based on a relative priority of each context and resource requirements of each context.

27. The method of claim 26 wherein the resource requirements comprises at least, in part, power consumption requirements.

28. The method of claim 26 wherein the power consumption requirements are dynamically adjusted based upon power constraints of said system.

29. The method of claim 29 wherein said order of execution is determined further based on at least one of system and user input available to said scheduling component.