Capacitor sharing surge protection circuit

• US 20090161281A1
• Filed: 12/21/2007
• Published: 06/25/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Maggiolino, Louis
• Granted Patent: US 7,679,878 B2
• Time in Patent Office: Days
• US Class Current: 361/111
• CPC Class Codes: H02H 1/0038 concerning the connection of the detecting means, e.g. for reducing their number
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T

Abstract

A capacitor sharing surge protection circuit for protecting multiple ports from harmful energy surges, such as electrostatic discharge (ESD) and cable discharge events (CDE), is provided. The protection circuit includes a plurality of diodes with respective cathodes and anodes. Each anode of the plurality of diodes is coupled to one of the plurality of ports. A bypass capacitor is coupled between the cathodes of the plurality of diodes and ground. In an embodiment, a bulk capacitor is further coupled between the cathodes of the plurality of diodes and ground.

Claims

1. A protection circuit, comprising:

a plurality of ports;

a plurality of diodes, each diode including a cathode and an anode, wherein each anode is coupled to one of the plurality of ports; and

a bypass capacitor coupled between the cathodes of the plurality of diodes and ground.

2. The circuit of claim 1, wherein the circuit is a Power over Ethernet (PoE) protection circuit.

3. The circuit of claim 2, wherein the plurality of ports are Ethernet ports.

4. The circuit of claim 1, further comprising a bulk capacitor coupled between the cathodes of the plurality of diodes and ground.

5. The circuit of claim 4, wherein the bulk capacitor is comprised of a plurality of bypass capacitors in a parallel combination.

6. The circuit of claim 1, wherein at least a part of the protection circuit is deposited on a substrate.

7. The circuit of claim 1, wherein at least a part of the protection circuit is deposited on a plurality of substrates.

8. The circuit of claim 1, further comprising a transient-voltage-suppression (TVS) diode coupled between the cathodes of the plurality of diodes and ground.