Multi-die Memory, Apparatus and Multi-die Memory Stack

• US 20090161401A1
• Filed: 12/24/2007
• Published: 06/25/2009
• Est. Priority Date: 12/24/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Barth, Roland, Scheideler, Dirk, Walthes, Wolfgang, Stecker, Johannes, Bilger, Christoph, Gregorius, Peter, Ruckerbauer, Hermann, Bruennert, Michael, Skerlj, Maurizio
• Granted Patent: US 8,120,958 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Claims

1. A multi-die memory, comprising:

a first die; and

a second die;

wherein the first die comprises a first group of memory banks;

wherein the second die comprises a second group of memory banks;

wherein the first group of memory banks and the second group of memory banks are coupled to a common memory interface configured to couple the multi-die memory with an external connection; and

wherein the first die and the second die and the common memory interface are arranged in a common package.

2. The multi-die memory according to claim 1, wherein the first die and the second die are stacked,

wherein the first group of memory bank is connected to the common memory interface via a die-to-die connection which is at least approximately perpendicular to a main surface of the stacked dies.

3. The multi-die memory according to claim 2, wherein the first die and the second die comprise through-substrate-vias to connect the first group of memory banks and the second group of memory banks to the common memory interface.

4. The multi-die memory according to claim 1, wherein the multi-die memory is configured such that address lines of the first bank group are separated from address lines of the second bank group with the exception of an interconnection between the first die and the second die.

5. The multi-die memory according to claim 1, wherein the multi-die memory is configured such that data lines of the first bank group are separated from data lines of the second bank group with the exception of an interconnection between the first die and the second die,

wherein the interconnection is coupled to the data lines of the first bank group and to the data lines of the second bank group.

6. The multi-die memory according to claim 1, wherein the multi-die memory comprises a die-to-die data path,

wherein the first group of memory banks comprises a group-internal data path that is coupled to the die-to-die data path to receive data from the die-to-die data path or to provide data to the die-to-die data path;

wherein the second group of memory banks comprises a group-internal data path that is coupled to the die-to-die data path to receive data from the die-to-die data path or to provide data to the die-to-die data path;

wherein the die-to-die data path is configured to be shared at least by the first group of memory banks and the second group of memory banks; and

wherein the group-internal data path of the first group of memory banks and the group-internal data path of the second group of memory banks are configured such that a data path line of the group-internal data path of the first group of memory channels can represent a different data value than a data path line of the group-internal data path of the second group of memory channels coupled to a same data path line of the die-to-die data path.

7. The multi-die memory according to claim 6, wherein the group-internal spine data path of the first group of memory banks is parallel to the group-internal spine data path of the second group memory banks;

and

wherein the group-internal spine data path of the first group of memory banks is decoupled from the group-internal spine data path of the second group of memory banks to be capable of carrying different data than the group-internal spine data path of the second group of memory banks.

8. The multi-die memory according to claim 1, wherein the multi-die memory comprises a die-to-die data path;

wherein the first group of memory banks comprises a group-internal data path which is coupled to the die-to-die data path to receive data from the die-to-die data path or to provide data to the die-to-die data path;

wherein the second group of memory banks comprises a group-internal data path which is coupled to the die-to-die data path to receive data from the die-to-die data path or to provide data to the die-to-die data path;

wherein the multi-die memory is configured such that the die-to-die data path carries on a shared data path line data for the first group of memory banks and data for a second group of memory banks; and

wherein the multi-die memory is configured such that the group-internal data path of the first group of memory banks carries only data for the first group of memory banks.

9. The multi-die memory according to claim 6, wherein the die-to-die data path is configured to carry a higher data rate than the group-internal data path.

10. The multi-die memory according to claim 1, wherein the multi-die memory comprises a third die;

wherein the third die comprises the common memory interface;

wherein the first die, the second die and the third die are assembled in the common package;

wherein the first group of memory banks is coupled to the common memory interface via a first die-to-die connection;

wherein the second group of memory banks is coupled to the common memory interface via a second die-to-die connection; and

wherein the first die-to-die connection is separate from the second die-to-die connection.

11. The multi-die memory according to claim 10, wherein the common memory interface is configured to selectively drive data to the first die-to-die connection or to the second die-to-die connection in dependence on whether an access to the first group of memory banks or an access to the second group of memory banks is requested.

12. The multi-die memory according to claim 10, wherein the common memory interface is configured to selectively forward data from the first die-to-die connection or from the second die-to-die connection to the external connection.

13. The multi-die memory according to claim 1, wherein the common memory interface is arranged on the first die or on the second die.

14. The multi-die memory according to claim 1, wherein the common memory interface is arranged on a dedicated interface die.

15. The multi-die memory according to claim 14, wherein the dedicated interface die comprises a different sequence of technological layers when compared to the first die and the second die.

16. The multi-die memory according to claim 1, wherein the multi-die memory comprises a plurality of dies;

wherein each of the dies comprises at least one group of memory banks; and

wherein only one of the dies comprises circuitry forming the common memory interface.

17. The multi-die memory according to claim 1, wherein a group of memory banks comprises at least two memory banks;

wherein different memory banks comprise separate memory arrays; and

wherein the memory banks are configured such that word lines of memory arrays of different memory banks can be activated independently.

18. The multi-die memory according to claim 1, wherein the common memory interface is configured to interface the first group of memory banks and the second group of memory banks to the external connection such that external characteristics of the multi-die memory match external electrically characteristics of a single die memory comprising a plurality of groups of memory banks arranged on a single die.

19. An apparatus, comprising:

first means for carrying a semi-conductor structure;

second means for carrying a semi-conductor structure;

first means for retaining data, wherein the first means for retaining data comprises a plurality of means for allowing independent activation of rows of means for storing individual data items, and wherein the first means for retaining data is arranged on the first means for carrying a semiconductor structure;

second means for retaining data, wherein the second means for retaining data comprises a plurality of means for allowing independent activation of rows of means for storing individual data items, and wherein the second means for retaining data is arranged on the first means for carrying a semi-conductor structure;

means for commonly interfacing the first means for retaining data and the second means for retaining data with means for providing an external connection; and

means for commonly housing the first means for carrying a semi-conductor structure, the second means for carrying a semi-conductor structure and the means for interfacing.

20. A multi-die memory stack, comprising:

a first die;

a second die; and

a third die;

wherein the first die comprises a first group of memory banks;

wherein the second die comprises a second group of memory banks;

wherein the third die comprises a common memory interface configured to couple the first group of memory banks and the second group of memory banks to a shared external connection;

wherein the first group of memory banks is coupled to the common memory interface via a first die-to-die connection;

wherein the second group of memory banks is coupled to the common memory interface via a second die-to-die connection; and

wherein the common memory interface is configured to selectively drive data received from the shared external connection to the first die-to-die connection or to the second die-to-die connection in dependence on whether the data received from the shared external connection are intended for the first group of memory banks or the second group of memory banks.

21. The multi-die memory stack according to claim 20, wherein the dies are stacked, and wherein at least one of the die-to-die connections is at least approximately perpendicular to a main surface of the stacked dies.

22. A multi-die memory stack, comprising:

a first die;

a second die; and

a third die;

wherein the first die comprises a first group of memory banks;

wherein the second die comprises a second group of memory banks;

wherein the third die comprises a common memory interface configured to couple the first group of memory banks and the second group of memory banks to a shared external connection;

wherein the first group of memory banks is coupled to the common memory interface via a first die-to-die connection;

wherein the second group of memory banks is coupled to the common memory interface via a second die-to-die connection; and

wherein the common memory interface is configured to selectively forward data from the first die-to-die connection or from the second die-to-die connection to the shared external connection.

23. The multi-die memory stack according to claim 22, wherein the dies are stacked, and wherein at least one of the die-to-die connections is at least approximately perpendicular to a main surface of the stacked dies.