INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION

• US 20090161415A1
• Filed: 12/21/2007
• Published: 06/25/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Majewski, Petra, Andres, Dieter, Ruster, Christian, Philipp, Jan Boris, Happ, Thomas, Ruf, Bernhard
• Granted Patent: US 7,646,632 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.

Claims

1. An integrated circuit comprising:

an array of resistance changing memory cells; and

a first circuit configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell, the pulse based on a reset current distribution for the array of memory cells.

2. The integrated circuit of claim 1, wherein the reset current distribution includes two segments;

and

wherein the pulse comprises two steps, each step based on a median reset current for a segment of the reset current distribution.

3. The integrated circuit of claim 1, wherein the reset current distribution includes three segments;

and

wherein the pulse comprises three steps, each step based on a median reset current for a segment of the reset current distribution.

4. The integrated circuit of claim 1, further comprising:

a second circuit configured to determine the reset current distribution for the array of memory cells.

5. The integrated circuit of claim 4, wherein the second circuit is configured to determine the reset current distribution in response to one of a power up of the array, a preset period of inactivity of the array, and an external signal.

6. The integrated circuit of claim 4, wherein the second circuit is configured to determine a set resistance distribution for the array, compare the set resistance distribution to a predefined level, and adjust the pulse based on the comparison.

7. The integrated circuit of claim 1, further comprising:

a configuration device configured to define parameters of the pulse.

8. The integrated circuit of claim 1, wherein the array of memory cells comprises an array of phase change memory cells.

9. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising;

an array of phase change memory cells; and

a write circuit configured to set a selected memory cell to a crystalline state by applying a set pulse to the selected memory cell, the set pulse based on a reset current distribution for the array of memory cells.

10. The system of claim 9, wherein the reset current distribution includes two segments;

and

wherein the set pulse comprises two steps, each step based on a median reset current for a segment of the reset current distribution.

11. The system of claim 9, wherein the reset current distribution includes three segments;

and

wherein the set pulse comprises three steps, each step based on a median reset current for a segment of the reset current distribution.

12. The system of claim 9, wherein the set pulse has a width less than 250 ns.

13. The system of claim 9, wherein the memory device further comprises:

a sense circuit configured to read data from the array; and

a controller configured to control the write circuit and the sense circuit.

14. A system comprising:

a test circuit; and

a memory device communicatively coupled to the test circuit, the memory device comprising;

an array of resistance changing memory cells; and

a configuration device for defining a set pulse;

wherein the test circuit is configured to determine a reset current distribution for the array of memory cells and program the configuration device to define the set pulse based on the reset current distribution.

15. The system of claim 14, wherein the reset current distribution includes two segments;

and

wherein the set pulse comprises two steps, each step based on a median reset current for a segment of the reset current distribution.

16. The system of claim 14, wherein the reset current distribution includes three segments;

and

wherein the set pulse comprises three steps, each step based on a median reset current for a segment of the reset current distribution.

17. The system of claim 14, wherein the test circuit is configured to determine a set resistance distribution for the array of memory cells, compare the set resistance distribution to a predefined level, and adjust the set pulse based on the comparison.

18. The system of claim 14, wherein the configuration device comprises one of fuses, anti-fuses, and a non-volatile memory.

19. A method for programming a memory, the method comprising:

determining a reset current distribution for an array of resistance changing memory cells;

dividing the reset current distribution into at least two segments;

determining a set pulse amplitude for each segment; and

combining the set pulse amplitudes into a decreasing stair step pulse.

20. The method of claim 19, wherein dividing the reset current distribution comprises dividing the reset current distribution into three segments.

21. The method of claim 19, wherein determining the set pulse amplitude for each segment comprises determining the set pulse amplitude for each segment based on a median reset current for each segment.

22. The method of claim 21, wherein determining the set pulse amplitude for each segment comprises multiplying the median reset current for each segment times a factor within a range of 0.2 to 0.7.

23. The method of claim 19, further comprising:

determining a set resistance distribution for the array;

comparing the set resistance distribution to a predefined level; and

adjusting the decreasing stair step pulse based on the comparison.