Regulation of Source Potential to Combat Cell Source IR Drop

• US 20090161433A1
• Filed: 12/20/2007
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Lee, Dana, Sekar, Deepak Chandra
• Granted Patent: US 7,764,547 B2
• Time in Patent Office: Days
• US Class Current: 365/185.120
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip'"'"'s ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.

Claims

1. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, the memory device comprising:

a page source line connectable to the source of each memory cell in a page;

an aggregate node coupled to individual page source lines of a structural block;

a source isolation switch coupled via said aggregate node to a page source line of a selected page for a memory operation; and

a source potential regulation circuit, including an active circuit element having a first input connected to a first reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node.

2. The memory device of claim 1, wherein the second input is connected to ground reference through a transistor controlled by the output of the active circuit element.

3. The memory device of claim 1, wherein the source isolation switch includes a transistor through which the aggregate node is connected to ground reference, the transistor controlled by the feedback loop

4. The memory device of claim 1, further including control circuitry whereby the feedback loop is connected to the aggregate node during sensing operations.

5. The memory device of claim 1, further comprising:

an associated bit line connectable to the drain of each memory cell of said selected page;

a bit line voltage supply for providing a predetermined bit line voltage to the associated bit line of each memory cell of said selected page for a sensing operation;

a word line connectable to the control gate of each memory cell of said selected page; and

word line voltage supply circuitry to provide a predetermined word line voltage for the word line of each memory cell of said selected page for said sensing operation,

wherein said first reference voltage is independent of the word line and bit line voltages during the sensing operation.

6. The memory device of claim 1, further comprising:

a pull-up element connectable to the aggregate node.

7. The memory device of claim 6, wherein the pull-up element is regulated by the active circuit element.

8. The memory device of claim 1, wherein the first reference voltage is in a range of from 0.5V to 1.0V.

9. The memory device of claim 1, wherein the first reference voltage is ground reference.

10. The memory device of claim 1, wherein the memory device has a plurality of planes and wherein said source potential regulation circuit is for a first of said planes, others of said planes having distinct source potential regulation circuits.

11. The memory device of claim 1, wherein the memory cells are organized according to a NAND type architecture.

12. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:

providing a page source line;

coupling the source of each memory cell of said page to said page line source line;

coupling the page source line to a structural block aggregate node for connection to a source voltage control circuit for sensing operation;

coupling the aggregate node to a feedback loop of a source potential regulation circuit including an active circuit element having a first input and having a second input connected to the feedback loop; and

applying a first reference voltage to said first input.

13. The method of claim 12, wherein the second input is connected to ground reference through a transistor, the method further comprising:

controlling said transistor by the output of the active circuit element.

14. The method of claim 12, wherein the source isolation switch includes a transistor through which the aggregate node is connected to ground reference, the method further comprising:

controlling the transistor by the feedback loop.

15. The method of claim 12, further comprising:

connecting the feedback loop to the aggregate node.

16. The method of claim 12, the memory device further having an associated bit line coupling to the drain of each memory cell of said page and a word line coupling to the control gate of each memory cell of said page, the method further comprising:

providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for the sensing operation; and

providing a predetermined word line voltage for the word line of each memory cell of said page for said sensing operation,

wherein said first reference voltage is independent of the word line and bit line voltages during said sensing operation.

17. The method of claim 12, further comprising:

connecting a pull-up element connectable to the aggregate node.

18. The method of claim 17, further comprising:

regulating the pull-up element by the active circuit element.

19. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, the memory device comprising:

a page source line connectable to the source of each memory cell in a page;

an aggregate node coupled to individual page source lines of a structural block;

a source isolation switch coupled via said aggregate node to a page source line of a selected page for a memory operation; and

a non-linear resistive element connectable between the aggregate node and ground reference.

20. The memory device of claim 19, wherein the non-linear resistive element is a diode.

21. The memory device of claim 19, further including control circuitry whereby the non-linear resistor element is connected to the aggregate node during sensing operations.

22. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:

providing a page source line;

coupling the source of each memory cell of said page to said page line source line;

coupling the page source line to a structural block aggregate node for connection to a source voltage control circuit for sensing operation; and

coupling the aggregate node to ground reference by a non-linear resistive element connectable.

23. The method of claim 22, wherein the non-linear resistive element is a diode.

24. The method of claim 22, further comprising:

connecting the non-linear resistor element to the aggregate node.