DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE

• US 20090161451A1
• Filed: 10/24/2008
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 7,983,099 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Claims

1. A method for setting an operating mode of a memory device, the method comprising:

powering up the memory device;

responding to a voltage of a port to provide a response after the memory device has completed power up; and

setting an operation mode of circuitry of the memory device in response to the response.

2. The method of claim 1, wherein the step of setting comprises:

selecting signals corresponding to the operating mode based on the response for use by the circuitry of the memory device.

3. The method of claim 2, wherein the step of selecting comprises:

detecting an absence of the voltage to provide a voltage response as the response, the voltage response corresponding to a complement of the response in a case where the absence of the voltage is undetected.

4. The method of claim 3, wherein the step of setting further comprises:

setting the operation mode of the circuitry in another operating mode in response to the complement of the response.

5. The method of claim 4, wherein the memory device has at least one other port, and the step of setting further comprises:

receiving a signal containing information at the at least one other port; and

configuring the at least one other port to receive the information contained in the signal in response to one of the response and the complement of the response, the circuitry operating in response to the information.

6. The method of claim 5, wherein the step of receiving comprises:

receiving the signal containing information corresponding to at least one of control information and data information at the at least on other port.

7. The method of claim 1, wherein powering up the memory device includes detecting a power supply voltage reaching a predetermined level.

8. The method of claim 7, wherein the voltage is the power supply voltage.

9. The method of claim 7, wherein the voltage of the port is detected when the power supply voltage reaches the predetermined level.

10. The method of claim 7, wherein the port includes an existing port used in the first operating mode, the existing port being unused in the second operating mode.

11. The method of claim 10, wherein a low logic level of the existing port is latched when the power supply voltage has reached the predetermined level.

12. The method of claim 11, wherein the existing port can be switched between high and low logic levels after the low logic level is latched.

13. The method of claim 1, wherein the port is unused in the first operating mode and the second operating mode.

14. The method of claim 1, wherein setting includes driving a mode signal to a first logic level when the voltage is detected on the port, the mode signal being driven to a second logic level when the voltage is undetected on the port.

15. The method of claim 14, wherein setting includes coupling control and data ports of the memory device to asynchronous circuits in response to the first logic level of the mode signal, and coupling the control and data ports of the memory device to synchronous circuits in response to the second logic level of the mode signal.

16. The method of claim 15, wherein setting further includes disconnecting the power supply voltage from the synchronous circuits in response to the first logic level of the mode signal, and disconnecting the power supply voltage from the asynchronous circuits in response to the second logic level of the mode signal.

17. The method of claim 15, wherein the asynchronous circuits includes an asynchronous command decoder for providing decoded asynchronous command signals, and a synchronous command decoder for providing decoded synchronous command signals.

18. The method of claim 17, wherein setting further includes selectively passing one of the decoded asynchronous command signals and the decoded synchronous command signals to control logic in response to the mode signal.

19. The method of claim 18, wherein the decoded asynchronous command signals and the decoded synchronous command signals are identical to each other.

20. A memory device configurable to operate in a first mode and a second mode, comprising:

ports for receiving one of a first function assignment corresponding to the first mode and a second function assignment corresponding to the second mode;

an interface and control circuit for receiving a command from at least one of the ports, and configurable for decoding the command in one of the first mode and the second mode, the command being decoded for controlling core circuits of the memory device; and

a mode detector connected to a selected port of the ports for configuring the interface and control circuit to decode the command in the first mode when the voltage supply is detected, and to decode the command in the second mode when the voltage supply is undetected.

21. The memory device of claim 20, wherein the interface and control circuit includes

synchronous circuits coupled to the ports for receiving the command and generating decoded synchronous command signals when the voltage supply is undetected by the mode detector;

asynchronous circuits coupled to the ports for receiving the command and generating decoded asynchronous command signals when the voltage supply is detected by the mode detector;

control logic for generating identical internal control signals in response to the decoded synchronous command signals and the decoded asynchronous command signals; and

,

a selector for selectively passing one of the decoded synchronous command signals and the decoded asynchronous command signals to the control logic in response to a detected state of the voltage supply.

22. The memory device of claim 21, wherein the mode detector includes

a voltage detector for providing a status signal when the voltage supply has reached a predetermined level, and

mode logic coupled to the selected port for driving a mode signal from a first logic level to a second logic level in response to the status signal while the selected port is biased to a voltage level other than the voltage supply.

23. The memory device of claim 22, wherein the synchronous circuits includes synchronous buffers coupled to each of the ports and a synchronous command decoder, and the asynchronous circuits includes asynchronous buffers coupled to each of the ports and an asynchronous command decoder.

24. The memory device of claim 23, wherein each port in the first function assignment and the second function assignment of a same type have common buffers functioning as both the synchronous buffers and the asynchronous buffers, where the type can be one of an input type and an output type.

25. The memory device of claim 24, wherein the interface and control circuit further includes signal path switches for selectively coupling each of the ports to the synchronous command decoder through the synchronous buffers in response to the first logic level of the mode signal, and for selectively coupling each of the ports to the asynchronous command decoder through the asynchronous buffers in response to the second logic level of the mode signal.

26. The memory device of claim 25, wherein the interface and control circuit further includes

first power switches for decoupling the voltage supply from the synchronous circuits in response to the second logic level of the mode signal, and

second power switches for decoupling the voltage supply from the asynchronous circuits in response to the first logic level of the mode signal.

27. The memory device of claim 22, wherein the mode logic includes a latch for maintaining the second logic level of the mode signal in response to the status signal.

28. The memory device of claim 20, wherein the selected port is a functional port used during normal operation of one of the first mode and the second mode.

29. The memory device of claim 20, wherein the selected port is a dedicated port unused during normal operation of both the first mode and the second mode.

30. A memory system comprising:

a memory controller for providing control signals having a first signal function assignment and second signal function assignment; and

a plurality of memory devices each configurable for receiving one of the first signal function assignment and the second signal function assignment in response to a port biased to a power supply voltage during a power up sequence, each of the plurality of memory devices configured for receiving the other of the first signal function assignment and the second signal function assignment when the port is biased to another power supply voltage during the power up sequence.

31. The memory device of claim 30, wherein the port is part of the first signal function assignment and is unused in the second function assignment.

32. The memory device of claim 30, wherein the port is unused in both the first signal function assignment and the second function assignment.

33. The memory device of claim 30, wherein the port is physically bonded to the power supply voltage.

34. The memory device of claim 30, wherein the port is statically held at the power supply voltage by a circuit.