TD-SCDMA UPLINK PROCESSING

• US 20090161647A1
• Filed: 08/19/2008
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Wang, Justin, Mestechkin, Russ, Nandipaku, Sanjay, Mathew, Deepak
• Application Number:
  US12/194,512
• Publication Number:
  US 20090161647A1
• Time in Patent Office: Days
• US Class Current: 370/342
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects

Abstract

A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set of time slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

Claims

1. An apparatus comprising:

at least two groups of registers, each group of register to store a set of time slot configuration parameters;

a storage to store a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot; and

a chip rate processing unit to process a stream of data over a plurality of time slots in which at each of the time slots, the chip rate processing unit is configured according to the set of time slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

2. The apparatus of claim 1 in which the chip rate processing unit performs at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission.

3. The apparatus of claim 1 in which each set of time slot configuration parameters comprise at least one of scrambling code, spreading code, spreading factor, and power control information.

4. The apparatus of claim 1 in which the chip rate processing unit operates in compliance with at least one of Code Division Multiple Access standard, Wideband Code Division Multiple Access standard, and Time Division-Synchronous Code Division Multiple Access standard.

5. The apparatus of claim 1 in which the at least one group of registers comprise five groups of registers to store five sets of time slot configuration parameters for configuring the chip rate processing unit to process five uplink time slots of a sub-frame.

6. The apparatus of claim 1 in which each group of registers can be accessed by the chip rate processing unit within one clock cycle.

7. The apparatus of claim 1 in which the sets of time slot configuration parameters are stored in the first storage in a sequence that is different from a sequence in which the sets of time slot configuration parameters are used to configure the chip rate processing unit.

8. The apparatus of claim 1, further comprising a multiplexer to multiplex the sets of time slot configuration parameters from the groups of registers, the multiplexer selecting one of the sets of time slot configuration parameters during each time slot based on the sequence of identifiers and sending the selected set of time slot configuration parameters to the chip rate processing unit.

9. The apparatus of claim 1 in which the storage that stores the sequence of identifiers comprises a first-in-first-out queue.

10. The apparatus of claim 1, further comprising a data processor to execute software to write the sets of time slot configuration parameters to the groups of registers and cause the identifiers to be written to the storage to control processing of the stream of data by the chip rate processing unit.

11. An apparatus comprising:

a first storage to store at least two sets of configuration parameters;

a second storage to store a sequence of identifiers each corresponding to one set of configuration parameters;

a special purpose data processor to process a stream of data in which the special purpose data processor is configured differently at different time periods according to the sets of configuration parameters associated with the sequence of identifiers; and

a general purpose data processor to write the sets of configuration parameters to the first storage and the sequence of identifiers to the second storage to control processing of the stream of data by the special purpose data processor.

12. The apparatus of claim 11 in which the special purpose data processor comprises an uplink chip rate processor.

13. The apparatus of claim 11 in which the first storage comprises groups of registers that can be accessed by the special purpose data processor through a multiplexer, each group of registers storing a set of configuration parameters.

14. The apparatus of claim 11 in which the first storage can be accessed by the special purpose data processor in one clock cycle.

15. The apparatus of claim 11 in which the second storage comprises a first-in-first-out queue.

16. The apparatus of claim 11 in which each identifier in the sequence of identifiers corresponds to a time slot in a sequence of time slots, and the same set of configuration parameters is reused for different time slots by having the sequence of identifiers include a same identifier multiple times.

17. The apparatus of claim 11 in which each set of configuration parameters comprise at least one of scrambling code, spreading code, spreading factor, and power control information.

18. A method comprising:

writing at least two sets of time slot configuration parameters to at least two groups of registers, each time slot configuration parameter having information on how data is to be processed by a chip rate processing unit during a time slot;

writing a sequence of identifiers to a storage, each identifier being associated with one of the groups of registers; and

at each of a plurality of time slots,

selecting one set of time slot configuration parameters stored in a group of registers according to the sequence of identifiers,

configuring the chip rate processing unit according to the selected set of time slot configuration parameters, and

processing data using the chip rate processing unit.

19. The method of claim 18 in which writing at least two sets of time slot configuration parameters comprises writing five sets of time slot configuration parameters for configuring the chip rate processing unit to process five uplink time slots of a sub-frame.

20. The method of claim 18 in which processing data using the chip rate processing unit comprises performing at least one of spreading data, scrambling data, and combining data from multiple physical channels to prepare the data for uplink transmission.

21. The method of claim 18 in which the chip rate processing unit operates in compliance with at least one of Code Division Multiple Access standard, Wideband Code Division Multiple Access standard, and Time Division-Synchronous Code Division Multiple Access standard.

22. The method of claim 18, further comprising multiplexing the sets of time slot configuration parameters to select one set of time slot configuration parameters for configuring the chip rate processing unit.

23. The method of claim 18, further comprising executing software in a data processor to specify what time slot configuration parameters are written to the first storage and which identifiers are written to the second storage.

24. The method of claim 18 in which writing a sequence of identifiers to the storage comprises writing the sequence of identifiers to a first-in-first-out queue.

25. The method of claim 18, further comprising writing a sequence of identifiers having a same identifier multiple times to the storage to re-use the set of time slot configuration parameters stored in the group of registers corresponding to the identifier without re-writing the set of time slot configuration parameters to the group of registers multiple times.

26. The method of claim 18 in which writing the time slot configuration parameters comprises writing at least one of scrambling code, spreading code, spreading factor, and power control information.

27. A method comprising:

processing a stream of data using a special purpose processor, and

using a general purpose processor to control configurations of the special purpose processor when processing a stream of data over time by

writing two or more sets of configuration parameters to a first storage,

writing a sequence of identifiers to a second storage, each identifier being associated with a set of configuration parameters, and

causing the special purpose processor to be configured differently according to various sets of configuration parameters at different time periods, using the sequence of identifiers to determine a sequence in which the different sets of configuration parameters are used to configure the special purpose processor.

28. The method of claim 27 in which the special purpose processor comprises a chip rate processor.

29. The method of claim 27 in which writing two or more sets of configuration parameters to a first storage comprises writing two or more sets of configuration parameters to two or more groups of registers, each group of register storing a set of configuration parameters.

30. The method of claim 27 in which writing the sequence of identifiers to a second storage comprises writing the sequence of identifiers to a first-in-first-out queue.

31. The method of claim 27 in which each set of time slot configuration parameters comprise at least one of scrambling code, spreading code, spreading factor, and power control information.

32. The method of claim 27 in which the general purpose processor executes software to determine which sets of configuration parameters are to be written to the first storage and which identifiers are to be written to the second storage to enable the special purpose processor to process the stream of data according to a telecommunications protocol.

33. The method of claim 32 in which the telecommunications protocol comprises at least one of Code Division Multiple Access standard, Wideband Code Division Multiple Access standard, and Time Division-Synchronous Code Division Multiple Access standard.

34. An apparatus comprising:

means for writing at least two sets of time slot configuration parameters to at least two groups of registers, each time slot configuration parameter having information on how data is to be processed by a chip rate processing unit during a time slot, and for writing a sequence of identifiers to a storage, each identifier being associated with one of the groups of registers; and

means for, at each of a plurality of time slots,

selecting one set of time slot configuration parameters stored in a group of registers according to the sequence of identifiers,

configuring the chip rate processing unit according to the selected set of time slot configuration parameters, and

processing data using the chip rate processing unit.