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HARDWARE IMPLEMENTATION OF THE SECURE HASH STANDARD

  • US 20090161863A1
  • Filed: 01/14/2009
  • Published: 06/25/2009
  • Est. Priority Date: 03/22/2001
  • Status: Abandoned Application
First Claim
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1. An integrated circuit for implementing a secure hash algorithm, comprising:

  • a data path configured to process an input message pursuant to the secure algorithm; and

    a controller configured to control operation of the data path;

    wherein the data path and the controller are implemented using hardware components.

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