HARDWARE IMPLEMENTATION OF THE SECURE HASH STANDARD

• US 20090161863A1
• Filed: 01/14/2009
• Published: 06/25/2009
• Est. Priority Date: 03/22/2001
• Status: Abandoned Application

• Current Assignee: QST Holdings LLC
• Original Assignee: QST Holdings LLC
• Inventors: SCHEUERMANN, Walter James
• Application Number:
  US12/353,267
• Publication Number:
  US 20090161863A1
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

An integrated circuit for implementing the secure hash algorithm is provided, According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller flirter includes an address control module and a finite state machine.

Claims

1. An integrated circuit for implementing a secure hash algorithm, comprising:

a data path configured to process an input message pursuant to the secure algorithm; and

a controller configured to control operation of the data path;

wherein the data path and the controller are implemented using hardware components.

2. An integrated circuit for implementing the secure hash algorithm, comprising:

a data path circuit comprising;

a memory configured to store a plurality of variables that are used to carry out the secure hash algorithm;

a first multiplexor coupled to the memory;

a first register coupled to the first multiplexor;

a shifter coupled to the first register;

an arithmetic logic unit coupled to the shifter and the first multiplexor;

a second register coupled to the arithmetic logic unit; and

a second multiplexor coupled to the second register, the memory and the arithmetic logic unit; and

a controller configured to control operation of the data path circuit, comprising;

an address control module; and

a finite state machine operable in conjunction with the address control module to generate a physical memory address for accessing the memory and a plurality of control bits, the physical memory address and the plurality of control bits are used to control operation of the data path circuit.