SECURITY STORAGE OF ELECTRONIC KEYS WITHIIN VOLATILE MEMORIES

• US 20090164699A1
• Filed: 02/15/2007
• Published: 06/25/2009
• Est. Priority Date: 04/10/2006
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Zachariasse, Frank, List, Frans, Mels, Arjan, De Jong, Hans, Wagner, Mathias, Tuyls, Pim, Vertregt, Maarten
• Granted Patent: US 8,199,912 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: H04L 9/0877 using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM]

Abstract

It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key. The integrated circuit (100) comprises a volatile memory (102) comprising predetermined data storage cells (102a), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory (104) having information stored upon regarding the predetermined data storage cells (102a). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells (102a).

Claims

1. A method for providing an electronic key within an integrated circuit including both a volatile memory and a non-volatile memory, the method comprising

starting up the integrated circuit,

reading the logical state of predetermined data storage cells assigned to the volatile memory, which data storage cells are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and

generating an electronic key by using the logical state of the predetermined data storage cells.

2. The method according to claim 1, further comprising

using a helper dataset stored in the non-volatile memory, wherein the helper dataset comprises information indicating the predetermined data storage cells.

3. The method according to claim 1, further comprising

using a further helper dataset stored in the non-volatile memory, wherein the further helper dataset comprises further information indicating at least some non-stable data storage cells assigned to the volatile memory, which non-stable data storage cells are characterized that with a plurality of start up procedures they respectively adopt randomly different logical states.

4. The method according to claim 1, further comprising

destroying the electronic key after it has been used.

5. The method according to claim 1, further comprising

identifying the predetermined data storage cells Ruby means of a training procedure.

6. The method according to claim 1, wherein

the predetermined data storage cells are randomly distributed within the volatile memory.

7. An integrated circuit for providing an electronic key, the integrated circuit comprising

a volatile memory comprising predetermined data storage cells, which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and

a non-volatile memory having information stored upon regarding the predetermined data storage cells,

wherein the electronic key is defined by the logical state of the predetermined data storage cell.

8. The integrated circuit according to claim 7, wherein

the volatile memory comprises non-stable data storage cells, which are characterized that with a plurality of start up procedures they respectively adopt randomly different logical states, and

the non-volatile memory have further information stored upon regarding the non-stable data storage cells.

9. The integrated circuit according to claim 7, wherein

the non-volatile memory comprises a ROM, a PROM, an EPROM, an EEPROM and/or a Flash memory.

10. The integrated circuit according to claim 7, wherein

the volatile memory comprises a RAM, a DRAM, and/or a SRAM.

11. The integrated circuit according to claim 7, wherein

the predetermined data storage cells are randomly distributed within the volatile memory.